Patents by Inventor Takeshi Nagase

Takeshi Nagase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11964838
    Abstract: A printing apparatus includes a printing unit configured to print an image on a sheet; a first exit path from which the sheet with the image printed thereon by the printing unit is discharged while being reversed; a second exit path from which the sheet with the image printed thereon by the printing unit is discharged without being reversed; and a switch member configured to be pivotably arranged so as to switch between the first exit path and the second exit path. The first exit path passes above a pivot center of the switch member, and the second exit path passes below the pivot center.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: April 23, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shinya Asano, Takeshi Koda, Toshiro Sugiyama, Waichiro Saiki, Tomohiro Suzuki, Ryo Kobayashi, Tomoyuki Nagase
  • Publication number: 20230220524
    Abstract: A multi-component system alloy includes titanium, zirconium, niobium, molybdenum, and tantalum, and further the multi-component system alloy includes at least one selected from the group consisting of hafnium, tungsten, vanadium, and chromium, wherein the alloy satisfies Mo equivalent ? 13.5, and the alloy is a single-phase solid solution, a two-phase solid solution, or an alloy in which a main phase is a solid solution phase.
    Type: Application
    Filed: May 26, 2021
    Publication date: July 13, 2023
    Inventors: Takayoshi Nakano, Takeshi Nagase, Aira Matsugaki
  • Patent number: 8503259
    Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Limited
    Inventors: Shogo Shibazaki, Shinkichi Gama, Hideyuki Negi, Takeshi Nagase, Chikahiro Deguchi, Yutaka Sekino
  • Patent number: 8143901
    Abstract: A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: March 27, 2012
    Assignee: Fujitsu Limited
    Inventors: Chikahiro Deguchi, Yutaka Sekino, Shogo Shibazaki, Shinkichi Gama, Takeshi Nagase, Hideyuki Negi
  • Patent number: 8020736
    Abstract: A spare tire cover supporting structure includes: a transverse rear door, provided on a vehicle; a spare tire cover, including a first end and a second end, the first end supported on the transverse rear door, the spare tire cover operable to cover a spare tire held on the transverse rear door; a mounting member, detachably mounting the second end on the transverse rear door; and a supporting member, provided on one of the transverse rear door and the second end of the spare tire cover. When the second end of the spare tire cover is mounted on the transverse rear door by the mounting member or the second end of the spare tire cover is detached from the transverse rear door, the supporting member positions the spare tire cover relative to the transverse rear door and restricts an opening movement of the spare tire cover.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: September 20, 2011
    Assignee: Mitsubishi Jidosha Kogyo Kabushiki Kaisha
    Inventor: Takeshi Nagase
  • Patent number: 7689836
    Abstract: An encryption/decryption processing unit performs encryption/decryption processing of data transmitted from a host system, and encryption/decryption processing of key data used for encryption/decryption of the data. A key data buffer temporarily stores encrypted key data. A key data buffer temporarily stores unencrypted key data. An external memory interface controls flash memory attached outside, and reads/writes encrypted key data stored in the key data buffer.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: March 30, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Takeshi Nagase, Shogo Shibazaki, Shinkichi Gama
  • Publication number: 20090296505
    Abstract: A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1?k?n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data.
    Type: Application
    Filed: March 17, 2009
    Publication date: December 3, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Shogo Shibazaki, Shinkichi Gama, Hideyuki Negi, Takeshi Nagase, Chikahiro Deguchi, Yutaka Sekino
  • Publication number: 20090300443
    Abstract: A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.
    Type: Application
    Filed: February 19, 2009
    Publication date: December 3, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Chikahiro Deguchi, Yutaka Sekino, Shogo Shibazaki, Shinkichi Gama, Takeshi Nagase, Hideyuki Negi
  • Publication number: 20080073389
    Abstract: A spare tire cover supporting structure includes: a transverse rear door, provided on a vehicle; a spare tire cover, including a first end and a second end, the first end supported on the transverse rear door, the spare tire cover operable to cover a spare tire held on the transverse rear door; a mounting member, detachably mounting the second end on the transverse rear door; and a supporting member, provided on one of the transverse rear door and the second end of the spare tire cover. When the second end of the spare tire cover is mounted on the transverse rear door by the mounting member or the second end of the spare tire cover is detached from the transverse rear doors the supporting member positions the spare tire cover relative to the transverse rear door and restricts an opening movement of the spare tire cover.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 27, 2008
    Inventor: Takeshi NAGASE
  • Publication number: 20070165864
    Abstract: An encryption/decryption processing unit performs encryption/decryption processing of data transmitted from a host system, and encryption/decryption processing of key data used for encryption/decryption of the data. A key data buffer temporarily stores encrypted key data. A key data buffer temporarily stores unencrypted key data. An external memory interface controls flash memory attached outside, and reads/writes encrypted key data stored in the key data buffer.
    Type: Application
    Filed: December 21, 2005
    Publication date: July 19, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi Nagase, Shogo Shibazaki, Shinkichi Gama
  • Publication number: 20070045361
    Abstract: A spare tire cover mounting structure includes a spare tire cover and a locking unit. The spare tire cover covers a spare tire supported by an outer wall portion of a door member. The locking unit includes an engagement portion provided in the spare tire cover and a locking mechanism to be engaged with the engagement portion. The locking mechanism includes a member to be engaged to be engaged with the engagement portion and an operating portion to be operated for releasing the engagement between the engagement portion and member to be engaged. The operating portion is disposed inside the outer wall portion and at a position where it can be operated in a state where the door member is closed.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 1, 2007
    Inventors: Hiroshi Aoyama, Hiroyasu Takeshita, Takeshi Nagase
  • Patent number: 7168829
    Abstract: A vehicle rear gate includes a gate panel, a garnish disposed on the gate panel, and a gate handle provided to the garnish. The gate handle can be turnable backward of a vehicle to open the gate panel. There is a stop lamp provided to the garnish, and a stop lamp attaching portion that reinforces the garnish.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: January 30, 2007
    Assignee: Mitsubishi Jidosha Kogyo Kabushiki Kaisha
    Inventor: Takeshi Nagase
  • Patent number: 7117966
    Abstract: An electrically-powered scooter including a front wheel, a rear wheel and a frame assembly. A handlebar assembly and a seat assembly are supported by the frame assembly. The frame assembly includes a left frame rail and a right frame rail spaced laterally from one another and extending between the handle bar assembly and the seat assembly. A battery support extends between the left and the right frame rails at a position intermediate the handle bar assembly and the seat assembly. A battery is supported by the battery support. In one arrangement, the battery support includes an enclosure defining a battery storage chamber. The enclosure includes a guide member configured to engage a guide recess of the battery to guide the battery into the battery storage chamber. In another arrangement, the battery may include a recharging port, an axis of which defines an oblique angle with an axis of the battery.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: October 10, 2006
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Hideo Kohda, Atsushi Koizumi, Ikuo Okamoto, Takeshi Nagase, Junji Terada
  • Publication number: 20040202000
    Abstract: A vehicle rear gate includes a gate panel, a garnish disposed on the gate panel, a gate handle provided to the garnish and being turnable backward of a vehicle to open the gate panel, a stop lamp provided to the garnish, and a stop lamp attaching portion that reinforces the garnish.
    Type: Application
    Filed: April 8, 2004
    Publication date: October 14, 2004
    Inventor: Takeshi Nagase
  • Publication number: 20040031632
    Abstract: An electrically-powered scooter including a front wheel, a rear wheel and a frame assembly. A handlebar assembly and a seat assembly are supported by the frame assembly. The frame assembly includes a left frame rail and a right frame rail spaced laterally from one another and extending between the handle bar assembly and the seat assembly. A battery support extends between the left and the right frame rails at a position intermediate the handle bar assembly and the seat assembly. A battery is supported by the battery support. In one arrangement, the battery support includes an enclosure defining a battery storage chamber. The enclosure includes a guide member configured to engage a guide recess of the battery to guide the battery into the battery storage chamber. In another arrangement, the battery may include a recharging port, an axis of which defines an oblique angle with an axis of the battery.
    Type: Application
    Filed: August 14, 2003
    Publication date: February 19, 2004
    Inventors: Hideo Kohda, Atsushi Koizumi, Ikuo Okamoto, Takeshi Nagase, Junji Terada
  • Patent number: 6643730
    Abstract: A memory controlling device is controlled by a CPU to enable information to be read from memory when the memory starts an operation. The memory is capable of retaining data during a power off state and the data is loaded when the memory starts an operation.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: November 4, 2003
    Assignee: Fujitsu Limited
    Inventors: Yoshiki Okumura, Yoshihiro Takamatsuya, Tomohiro Hayashi, Shinkichi Gama, Takeshi Nagase
  • Patent number: 6625712
    Abstract: The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information of memory areas which are data storage destinations designated by a logical address issued by a host device. After an initializing process, the host device is immediately notified of canceling of a busy state, without production of the memory management table. Alternatively, only a part of the memory management table is produced and the host device is notified of the canceling of the busy state. After that, until the host device issues a process request, or when the host device is issuing a process request, an incomplete part of the memory management table is completed. Thus, the memory management table can be completed.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: September 23, 2003
    Assignee: Fujitsu Limited
    Inventors: Shogo Shibazaki, Takeshi Nagase
  • Patent number: 6449681
    Abstract: A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch circuits which store data in response to upper and lower buffer access signals, and a first detection circuit which detects whether data latched by the latch circuits match. A modifying circuit inputs data to the first and second latches or inputs inverted data to the first and second latches when one of the upper and lower buffer access signals is generated and the detection circuit detects a match. In this manner, the buffer access control circuit is used to update an address one by one, without the use of a delay circuit when consecutively accessing the upper and lower buffers.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: September 10, 2002
    Assignee: Fujitsu Limited
    Inventors: Shinkichi Gama, Takeshi Nagase, Yoshiki Okumura, Tomohiro Hayashi, Yoshihiro Takamatsuya
  • Patent number: 6418501
    Abstract: A memory card realizes two interface standards. The memory card includes an input terminal receiving a grounded or open-circuited signal from a host unit when using the memory card in conformance with a first interface standard, and receiving a binary signal from the host unit when using the memory card in conformance with a second interface standard, a first circuit acquiring standard information which indicates the first or second interface standard, from a signal issued from the host unit, a second circuit outputting a high-level voltage when using the memory card in conformance with the first interface standard and outputting a high-impedance signal when using the memory card in conformance with the second interface standard, depending on the standard information acquired by the first circuit, and a resistor coupling an output of the second circuit and the input terminal.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: July 9, 2002
    Assignee: Fujitsu Limited
    Inventors: Shinkichi Gama, Yoshiki Okumura, Takeshi Nagase, Tomohiro Hayashi, Yoshihiro Takamatsuya
  • Publication number: 20020032830
    Abstract: A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch circuit which store data in response to upper and lower buffer access signals, and a first detection circuit which detects whether data latched by the latch circuits match. A modifying circuit inputs data to the first and second latches or inputs inverted data to the first and second latches when one of the upper and lower buffer access signals is generated and the detection circuit detects a match.
    Type: Application
    Filed: November 21, 2001
    Publication date: March 14, 2002
    Applicant: Fujitsu Limited
    Inventors: Shinkichi Gama, Takeshi Nagase, Yoshiki Okumura, Tomohiro Hayashi, Yoshihiro Takamatsuya