Abstract: A circuit for enabling a chip, usable for both a first device capable of having m chips and a second device having more than m chips, includes a first generation unit which generates a chip-enable signal that includes a bit pattern of m bits for enabling one of the m chips indicated by a chip number, a second generation unit which generates a chip-enable generation signal that is to be decoded into a chip-enable signal of at least 2m bits for enabling one of the more than m chips indicated by the chip number, the chip-enable generation signal including a bit pattern identical to the bit pattern of m bits when the chip number is equal to a specific number, and a selection unit which selects and outputs the chip-enable signal generated by the first generation unit when the circuit is used for the first device, and selects and outputs the chip-enable generation signal generated by the second generation unit when the circuit is used for the second device.

Abstract: A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch circuits which store data in response to upper and lower buffer access signals, and a first detection circuit which detects whether data latched by the latch circuits match. A modifying circuit inputs data to the first and second latches or inputs inverted data to the first and second latches when one of the upper and lower buffer access signals is generated and the detection circuit detects a match. In this manner, the buffer access control circuit is used to update an address one by one, without the use of a delay circuit when consecutively accessing the upper and lower buffers.

Abstract: A circuit for enabling a chip, usable for both a first device capable of having m chips and a second device having more than m chips, includes a first generation unit which generates a chip-enable signal that includes a bit pattern of m bits for enabling one of the m chips indicated by a chip number, a second generation unit which generates a chip-enable generation signal that is to be decoded into a chip-enable signal of at least 2m bits for enabling one of the more than m chips indicated by the chip number, the chip-enable generation signal including a bit pattern identical to the bit pattern of m bits when the chip number is equal to a specific number, and a selection unit which selects and outputs the chip-enable signal generated by the first generation unit when the circuit is used for the first device, and selects and outputs the chip-enable generation signal generated by the second generation unit when the circuit is used for the second device.

Abstract: The present invention relates to a method of producing a memory management table that controls memories having a function to hold data at a time of power cut-off and manages identifier information of memory areas which are data storage destinations designated by a logical address issued by a host device. After an initializing process, the host device is immediately notified of canceling of a busy state, without production of the memory management table. Alternatively, only a part of the memory management table is produced and the host device is notified of the canceling of the busy state. After that, until the host device issues a process request, or when the host device is issuing a process request, an incomplete part of the memory management table is completed. Thus, the memory management table can be completed.

Abstract: A semiconductor memory device has a memory space which includes blocks and each of the blocks includes sectors. The sectors have a data storing region and a flag region. Data stored in a sector is marked as valid or erased, depending on the flags in the flag region. If an even number of the flags in the flag region have a logical value of 1, the data is considered to be erased. The data in each sector may be erased and unerased a number of times, by sequentially altering the value of the flags in the flag region. Data stored in the memory may be erased on a sector-by-sector basis.

Abstract: Several embodiments of prime mover-assisted pedal-operated vehicles, such as a bicycle. In each embodiment, both the prime mover and the pedal mechanism drive the rear wheel through a common transfer shaft. The transfer shaft is disposed vertically above the pedal-operated crankshaft axis so as to improve the ground clearance and simplify the overall construction of the bicycle. The transmission arrangement is such that the prime mover transmission ratios are always in a step-down condition while the pedal-operated crankshaft drives the transfer shaft through a step-up transmission. Various embodiments of improved torque sensors are also employed so as to provide smooth transition and smooth feel to the rider.

Abstract: Motorcycle having a head pipe for mounting a front fork assembly for movement about a steering axis which is inclined rearwardly with respect to a vertical line to define a caster angle. The front fork assembly has an axis which is inclined rearwardly with respect to a vertical line by an angle smaller than the caster angle. The front fork assembly supports the front axle along the front side at a position upwardly distant from the lower end thereof.