Patents by Inventor Takeshi Nakano

Takeshi Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8335125
    Abstract: A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Nakano, Hiroshi Nakamura, Koji Hosono
  • Patent number: 8250447
    Abstract: A bit register is restored to the initial state thereof irrespective of the state of the bit register even when a convolution encoder includes a circular section. The convolution encoder comprises an input data acquiring section (F11) for acquiring input data; an encoding object data generating section (F10) for generating encoding object data on the basis of the input data; a storage section (M10) for storing data corresponding to the encoding object data; a mod2 adder (S10) for performing convolution processing of the encoding object data on the basis of the data stored in the storage section (M10); and a switching section (F12) for switching at a prescribed timing the encoding object data generated by the encoding object data generating section (F10) from data based on the input data to data based on the data stored in the storage section (M10); wherein the data stored in the storage section (M10) are data obtained as a result of the convolution processing.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: August 21, 2012
    Assignee: Kyocera Corporation
    Inventors: Mitsuharu Senda, Youhei Murakami, Takeshi Nakano, Masamitsu Nishikido
  • Publication number: 20120182953
    Abstract: In a base station device 12 of an OFDMA mobile communication system, a frequency band storage unit 22 stores multiple frequency bands allocatable to mobile station devices, respectively, in association with predetermined conditions related to communication quality. A communication quality acquisition unit 37 acquires communication quality in communication with each of the mobile station devices. A frequency allocator 24 selects any one of the frequency bands from the frequency band storage unit 22 on the basis of the communication quality acquired by the communication quality acquisition unit 37, and notifies the mobile station device of channel information indicating the selected frequency band. Then, the mobile station device communicates with the base station device 12 in the frequency band indicated by the channel information notified by the frequency allocator 24 in the base station device 12.
    Type: Application
    Filed: March 26, 2012
    Publication date: July 19, 2012
    Applicant: KYOCERA CORPORATION
    Inventors: Youhei MURAKAMI, Masamitsu NISHIKIDO, Takeshi NAKANO, Yutaka OOTSUKI
  • Publication number: 20120165553
    Abstract: [Problem to be Solved] An immunostimulant highly safe and administrable for a long period of time as well as a pharmaceutical composition containing the immunostimulant as an active ingredient and drink or food products for immunostimulation are developed and provided. [Solution] An immunostimulant containing a compound represented by the following general formula (I) or a pharmaceutically acceptable salt thereof as an active ingredient is provided. R1 is a hydrogen atom or a substituted or unsubstituted alkyl group having 1 to 6 carbon atoms, R2 to R5 are independently a hydrogen atom, or a substituted or unsubstituted lower alkyl or lower acyl group, X is —(CH2)2—, —(CH2)3—, —(CH2)4—, —CO—CH2—, —CO—(CH2)2—, —CO—(CH2)3—, —CH2—CO—CH2—, —CO—O—CH2—, —CO—O—(CH2)2—, —O—CO—CH2—, —O—CO—(CH2)2—, —CH2—O—CH2—, —CH2—O—(CH2)2—, —O—CH2—, —O—(CH2)2—, —O—(CH2)3—, —NHY—CO—CH2—, —NHYCO—(CH2)2—, —CO—NHY—CH2— or —CO—NHY—(CH2)2—, Y herein is a hydrogen atom or a lower alkyl group.
    Type: Application
    Filed: December 12, 2011
    Publication date: June 28, 2012
    Applicant: RIKEN
    Inventors: Kenji Ogawa, Takeshi Nakano
  • Patent number: 8182949
    Abstract: A polymer electrolyte membrane comprising as a main ingredient a block copolymer (P) which comprises, as its constituents, a vinyl alcoholic polymer block (A) and a polymer block (B) having ion-conducting groups, which block copolymer (P) is cross-linking treated, and a membrane-electrode assembly and a fuel cell using the polymer electrolyte membrane, respectively. Preferred as polymer block (B) is one having a styrene or vinylnaphthalene skeleton or a 2-(meth)acrylamido-2-methylpropane skeleton. The ion-conducting group includes a sulfonic acid group, a phosphonic acid group or the like.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: May 22, 2012
    Assignee: Kuraray Co., Ltd.
    Inventors: Hiroyuki Ohgi, Tomohiro Ono, Shinji Nakai, Takeshi Nakano, Takeshi Kusudou, Naoki Fujiwara
  • Publication number: 20120044766
    Abstract: A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.
    Type: Application
    Filed: October 31, 2011
    Publication date: February 23, 2012
    Inventors: TAKESHI NAKANO, Hiroshi Nakamura, Koji Hosono
  • Patent number: 8107301
    Abstract: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: January 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Takeshi Nakano
  • Publication number: 20110317055
    Abstract: According to one embodiment, a third optical black portion is arranged in parallel with a first optical black portion in a row direction and in parallel with a second optical black portion in column direction. At least one of the vertical line correction circuit and the horizontal line correction circuit adds/subtracts arithmetic average of the third black level signal generated by the third optical black portion.
    Type: Application
    Filed: March 16, 2011
    Publication date: December 29, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiko NOZAKI, Takeshi NAKANO, Junichi HOSOKAWA
  • Patent number: 8077523
    Abstract: A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: December 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Nakano, Hiroshi Nakamura, Koji Hosono
  • Publication number: 20110300469
    Abstract: An electrolyte membrane having a structure wherein fine rubber particles having substantially no ion-conducting group and having an average particle size of 20 nm to 1 ?m are uniformly dispersed in a matrix including a resin component having ion-conducting group. The electrolyte membrane has high bonding ability to electrodes and does not cause cracks and ruptures because it is kept flexible even under low humid or absolutely dried condition, in addition, shows high ion conductivity even under low humid or absolutely dried condition because the matrix having ion-conducting groups are continuous.
    Type: Application
    Filed: February 12, 2010
    Publication date: December 8, 2011
    Applicant: Kuraray Co., Ltd.
    Inventors: Tomohiro Ono, Takeshi Nakano, Taketomo Yamashita, Keiji Kubo, Nozomu Sugoh
  • Patent number: 8025313
    Abstract: Disclosed is a suspension subframe structure of a vehicle, which is capable of improving the overall rigidity of a suspension subframe to effectively receive input loads from suspension arms, while reducing the overall weight of the suspension subframe.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: September 27, 2011
    Assignees: Mazda Motor Corporation, Y-Tec Corporation
    Inventors: Masaaki Tanaka, Katsuyuki Komiya, Shin Murata, Norihisa Adachi, Yukihito Itami, Hitoshi Nagai, Takeshi Nakano
  • Publication number: 20110225674
    Abstract: This invention provides a transformed plant or alga with increased chlorophyll, comprising an overexpressed foreign DNA which codes for a chloroplast protein BPG2 or a homologue thereof, and a method for producing the transformed plant or alga.
    Type: Application
    Filed: March 15, 2010
    Publication date: September 15, 2011
    Applicant: RIKEN
    Inventors: Takeshi Nakano, Tadao Asami, Ayumi Yamagami, Setsuko Shimada, Minami Matsui
  • Patent number: 8012628
    Abstract: This invention relates to an electrochemical device which comprises a molding containing as a main ingredient a copolymer (Z) and at least two mutually insulated electrodes in joint with the molding, wherein the copolymer (Z) comprises a polymer block (A) having as a main unit an aromatic vinyl compound unit and a polymer block (B) being incompatible with the polymer block (A), and has ion-conducting groups on the polymer block (A). The electrochemical device of the invention can be used particularly as an actuator device.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: September 6, 2011
    Assignee: Kuraray Co., Ltd.
    Inventors: Toshinori Kato, Tomohiro Ono, Shinji Nakai, Takeshi Nakano, Hiroyuki Ogi
  • Publication number: 20110182125
    Abstract: A semiconductor memory device in accordance with an embodiment comprises a memory cell array and an erase voltage generating circuit. The memory cell array is configured as an arrangement of nonvolatile memory cells. The erase voltage generating circuit is configured to generate an erase voltage for performing data erase of the memory cell array. The erase voltage generating circuit is configured to set, in a data erase mode where the erase voltage is applied to a selected region of the memory cell array in a plurality of erase cycles, a rise waveform of the erase voltage in an initial stage of the plurality of erase cycles to be less steep than a rise waveform of the erase voltage in subsequent cycles.
    Type: Application
    Filed: September 16, 2010
    Publication date: July 28, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mikihiko ITOH, Takeshi Nakano, Michio Nakagawa
  • Publication number: 20100329017
    Abstract: According to one embodiment, a semiconductor device includes a first voltage generator, a second voltage generator, a first MOS transistor, and a controller. The first voltage generator outputs a first voltage to a first node. The second voltage generator outputs a second voltage to a second node. The first MOS transistor is capable of short-circuiting the first node and second node. The controller performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor. The controller controls a period in which the first MOS transistor is kept in an on state based on time.
    Type: Application
    Filed: June 24, 2010
    Publication date: December 30, 2010
    Inventors: Takeshi NAKANO, Mikio Ogawa
  • Patent number: 7849357
    Abstract: A semiconductor memory device has a semiconductor memory which includes the first central management block storing an address translation table, a free table for registering only an effective block address, the first bad block table, and a reserved table, and a controller configured to control a substitution block address acquired from the reserved table to substitute a bad block address when the bad block address is generated in the address translation table.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: December 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeshi Nakano
  • Publication number: 20100233569
    Abstract: A multilayer electrolyte membrane for polymer electrolyte fuel cells, consisting of a laminate of at least two polymer electrolyte membranes at least one of which membranes comprises a block copolymer (I) which comprises, as its constituents, a polymer block (A) having as a main unit an aromatic vinyl compound unit and a flexible polymer block (B), and has ion-conducting groups on polymer block (A); and a membrane electrode assembly and a polymer electrolyte fuel cell. The multilayer membrane is economical, mild to the environment, and has high ion conductivity and high methanol barrier properties, together. It is preferred, from the object, that at least two of the constitutive electrolyte membranes comprise block copolymer (I), and/or at least one of the constitutive electrolyte membranes has an ion exchange capacity of 0.7 meq/g or more and at least one of them has an ion exchange capacity of less than 0.7 meq/g.
    Type: Application
    Filed: January 18, 2007
    Publication date: September 16, 2010
    Applicant: KURARAY CO., LTD
    Inventors: Tomohiro Ono, Shinji Nakai, Masahiro kawasaki, Takeshi Nakano, Hiroyuki Ogi
  • Publication number: 20100167159
    Abstract: A polymer electrolyte membrane comprising as a main ingredient a block copolymer which comprises, as its constituents, a polymer block (A) having as a main unit an aromatic vinyl compound unit and a polymer block (B) forming a flexible phase, and has ion-conducting groups on the polymer block (A), said aromatic vinyl compound unit being such that the hydrogen atom bonded to the ?-carbon atom is non-replaced or replaced with an alkyl group or an aryl group optionally having substituent(s), and at least one of hydrogen atoms directly bonded to the aromatic ring is replaced with an alkyl group; and a membrane electrode assembly and a polymer electrolyte fuel cell both of which uses it. The polymer block (A) can have a restraining phase, and/or can be cross-linked.
    Type: Application
    Filed: February 5, 2007
    Publication date: July 1, 2010
    Applicant: Kuraray Co., Ltd
    Inventors: Tomohiro Ono, Shinji Nakai, Hiroyuki Ogi, Takeshi Nakano
  • Publication number: 20100159353
    Abstract: Disclosed are: a polymer electrolyte which comprises, as the main component, a block/graft copolymer comprising, as constituent components, polymer blocks (A), (B) and (C) which cause phase-separation from one another, wherein the polymer block (A) comprises a vinyl compound unit as the main repeating unit and has an ion-conductive group, the polymer block (B) comprises a vinyl compound unit capable of forming a flexible phase as the main repeating unit and forms a flexible phase, and the polymer block (C) comprises a styrene derivative unit carrying an alicyclic hydrocarbon group having a polycyclic structure as the main repeating unit and forms a restrained phase; a membrane; a membrane-electrode assembly; and a solid polymer fuel cell.
    Type: Application
    Filed: May 30, 2008
    Publication date: June 24, 2010
    Applicants: Kuraray Co., Ltd, Tokyo Institute of Technology
    Inventors: Hiroyuki Ohgi, Tomohiro Ono, Shinji Nakai, Takeshi Nakano, Takashi Ishizone
  • Publication number: 20100098997
    Abstract: A polymer electrolyte membrane comprising as a main ingredient a block copolymer (P) which comprises, as its constituents, a vinyl alcoholic polymer block (A) and a polymer block (B) having ion-conducting groups, which block copolymer (P) is cross-linking treated, and a membrane-electrode assembly and a fuel cell using the polymer electrolyte membrane, respectively. Preferred as polymer block (B) is one having a styrene or vinylnaphthalene skeleton or a 2-(meth)acrylamido-2-methylpropane skeleton. The ion-conducting group includes a sulfonic acid group, a phosphonic acid group or the like.
    Type: Application
    Filed: January 11, 2008
    Publication date: April 22, 2010
    Applicant: Kuraray Co., Ltd.
    Inventors: Hiroyuki Ohgi, Tomohiro Ono, Shinji Nakai, Takeshi Nakano, Takeshi Kusudou, Naoki Fujiwara