Abstract: In a base station device 12 of an OFDMA mobile communication system, a frequency band storage unit 22 stores multiple frequency bands allocatable to mobile station devices, respectively, in association with predetermined conditions related to communication quality. A communication quality acquisition unit 37 acquires communication quality in communication with each of the mobile station devices. A frequency allocator 24 selects any one of the frequency bands from the frequency band storage unit 22 on the basis of the communication quality acquired by the communication quality acquisition unit 37, and notifies the mobile station device of channel information indicating the selected frequency band. Then, the mobile station device communicates with the base station device 12 in the frequency band indicated by the channel information notified by the frequency allocator 24 in the base station device 12.

Abstract: A radio base station 10 communicates with a mobile station by use of an OFDM scheme while using a signal as a transmission unit, the signal including an effective period for transmitting a data signal and a redundancy period for transmitting redundancy data based on the data signal transmitted during the effective period. The radio base station 10 measures an interference level of a signal transmitted from the mobile station and then changes the length of the redundancy period of the signal transmitted via a communication channel used for communications with the mobile station.

Abstract: A bit register is restored to the initial state thereof irrespective of the state of the bit register even when a convolution encoder includes a circular section. The convolution encoder comprises an input data acquiring section (F11) for acquiring input data; an encoding object data generating section (F10) for generating encoding object data on the basis of the input data; a storage section (M10) for storing data corresponding to the encoding object data; a mod2 adder (S10) for performing convolution processing of the encoding object data on the basis of the data stored in the storage section (M10); and a switching section (F12) for switching at a prescribed timing the encoding object data generated by the encoding object data generating section (F10) from data based on the input data to data based on the data stored in the storage section (M10); wherein the data stored in the storage section (M10) are data obtained as a result of the convolution processing.

Abstract: A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

Abstract: Disclosed is a suspension subframe structure of a vehicle, which is capable of improving the overall rigidity of a suspension subframe to effectively receive input loads from suspension arms, while reducing the overall weight of the suspension subframe.

Abstract: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.

Abstract: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.

Abstract: A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.

Abstract: This invention relates to an electrochemical device which comprises a molding containing as a main ingredient a copolymer (Z) and at least two mutually insulated electrodes in joint with the molding, wherein the copolymer (Z) comprises a polymer block (A) having as a main unit an aromatic vinyl compound unit and a polymer block (B) being incompatible with the polymer block (A), and has ion-conducting groups on the polymer block (A). The electrochemical device of the invention can be used particularly as an actuator device. The electrochemical device or actuator device of the invention can be actuated swiftly; is excellent in industrial economical efficiency; has only a low influence on the environment; holds self-standing properties; and is excellent in mechanical strength.

Abstract: A semiconductor memory device has a semiconductor memory which includes the first central management block storing an address translation table, a free table for registering only an effective block address, the first bad block table, and a reserved table, and a controller configured to control a substitution block address acquired from the reserved table to substitute a bad block address when the bad block address is generated in the address translation table.

Abstract: Comparators compare the amplitudes of a DPD tracking error signal indicating the phase difference between the detection signals supplied from a photodetector, and a PP tracking error signal indicating the level difference between the detection signals with the reference values, respectively. A gain control amplifier mutes a tracking error signal with the maximum amplitude smaller than a reference value.

Abstract: A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.

Abstract: A data recording system of a semiconductor integrated circuit device having a memory area is disclosed. The semiconductor integrated circuit device is equipped with a memory area that includes a binary area and a multi-level area. The semiconductor integrated circuit device records, in the binary area, data transmitted from a host device as binary data. Further, when no access is provided from the host device, the semiconductor integrated circuit device copies, to the multi-level area, the data recorded in the binary area as multi-level data.

Abstract: A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.

Abstract: There is disclosed is a method comprising surface-processing a Sn based, Sn alloy based or Sn—Zn alloy based solder particle (1), applied as a coating, such as by electrical plating or melt plating, to the surface of a metal material, such as iron, a steel plate or copper, with a phosphate and a silicium containing compound, to form a protective film (2). There are also disclosed a solder material (6) in which a protective film (2) formed of a phosphate and a silicium containing compound is formed on the surface of the Sn—Zn based solder particle (1), and a solder paste formed of this solder material (6) and the flux.

Abstract: A Differential Phase Detecting (DPD) tracking error generating section generates a DPD tracking error signal from a plurality of sense signals supplied from an optical sensor. A Push Pull (PP) tracking error generating section generates a PP tracking error signal from a plurality of sense signals supplied from the optical sensor. The amplitude of each of the DPD tracking error signal and PP tracking error signal is adjusted suitably under the control of a CPU. The suitably adjusted signals are added by an adder, thereby generating a tracking error signal.

Abstract: A semiconductor integrated circuit device is disclosed, which incorporates a mask ROM of a contact program scheme in which a drain contact of each of transistors which constitute a memory cell array is connected to a bit line through an interconnecting pattern and a via plug, wherein a plurality of via plugs are connected to a same bit line and continuously adjacently arranged in a bit line direction, a plurality of interconnecting patterns are arranged in association with the plurality of via plugs, and at least two continuously adjacent via plugs of the plurality of via plugs are commonly connected to each other by a common connecting wiring layer extending in the bit line direction through the interconnecting patterns in association with the at least two adjacent via plugs.

Abstract: A trench isolation region is formed in a surface region of a semiconductor substrate to form a MOS type element region. A mask layer having an opening portion is formed on the semiconductor layer, the opening portion continuously ranging on the entire surface of the MOS type element region and on part of the trench isolation region provided around the MOS type element region. A first impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated in the semiconductor layer under the bottom surface of the shallow trench isolation region. A second impurity ion is implanted into the entire surface via the mask layer to form a peak of the impurity profile is situated on the midway of the depth direction of the trench isolation region. Then, the first and second impurity ions are activated.

Abstract: Comparators compare the amplitudes of a DPD tracking error signal indicating the phase difference between the detection signals supplied from a photodetector, and a PP tracking error signal indicating the level difference between the detection signals with the reference values, respectively. A gain control amplifier mutes a tracking error signal with the maximum amplitude smaller than a reference value.

Abstract: There is provided a disk device including a detector section which generates detection signals according to reflected lights of laser lights emitted on a disk, a removing section which detects detrack components which have failed to detect recording information on the disk from the detection signals and removes and outputs the same from the detection signals, and a processing section which applies a predetermined processing on the basis of signals obtained by removing detrack components from the detection signals, so that erroneous address information on CAPA which has been failed to read or the like can be removed, thereby improving reading accuracy of the disk.