Patents by Inventor Takeshi Okagaki
Takeshi Okagaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128268Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: ApplicationFiled: December 11, 2023Publication date: April 18, 2024Inventors: Krishna Kumar BHUWALKA, Kyoung Min CHOI, Takeshi OKAGAKI, Dong Won KIM, Jong Chol KIM
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Publication number: 20240096960Abstract: An integrated circuit device includes a back side interconnection structure extending in a first horizontal direction. An active substrate includes a fin-type active area extending in the first horizontal direction on the back side interconnection structure. A metal silicide film is between the back side interconnection structure and the active substrate. A plurality of gate structures extends in a second horizontal direction perpendicular to the first horizontal direction on the active substrate. A first source/drain area and a second source/drain area are spaced apart from each other in the first horizontal direction with the plurality of gate structures therebetween on the active substrate. The first source/drain area directly contacts the active substrate. The second source/drain area is spaced apart from the active substrate and insulated from the active substrate.Type: ApplicationFiled: August 29, 2023Publication date: March 21, 2024Inventors: Seunghyun SONG, Minsuk Kim, Pilkwang Kim, Takeshi Okagaki, Geunmyeong Kim, Ahyoung kim, Yoonsuk Kim
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Patent number: 11876097Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: GrantFiled: August 6, 2021Date of Patent: January 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Krishna Kumar Bhuwalka, Kyoung Min Choi, Takeshi Okagaki, Dong Won Kim, Jong Chol Kim
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Publication number: 20230261079Abstract: Disclosed are semiconductor devices and fabrication methods thereof. The semiconductor device includes a substrate including first and second regions, a device isolation pattern in the substrate, a lower separation dielectric pattern on the first region of the substrate, first channel patterns on the lower separation dielectric pattern, a first gate electrode on the first channel patterns and including a first gate part between the lower separation dielectric pattern and a lowermost first channel pattern, and first source/drain patterns on opposite sides of the first gate electrode and in contact with lateral surfaces of the first channel patterns. A bottom surface of the lower separation dielectric pattern is at a level higher than or equal to that of a bottom surface of the device isolation pattern. A top end of the lower separation dielectric pattern is at a level higher than that of a bottom surface of the first gate part.Type: ApplicationFiled: November 15, 2022Publication date: August 17, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Seunghyun SONG, Pilkwang KIM, Joohyung YOU, Sungmin KIM, Yonghee PARK, Young-Seok SONG, Takeshi OKAGAKI
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Publication number: 20210366910Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: ApplicationFiled: August 6, 2021Publication date: November 25, 2021Inventors: Krishna Kumar BHUWALKA, Kyoung Min CHOI, Takeshi OKAGAKI, Dong Won KIM, Jong Chol KIM
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Patent number: 11133311Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: GrantFiled: March 20, 2019Date of Patent: September 28, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Krishna Kumar Bhuwalka, Kyoung Min Choi, Takeshi Okagaki, Dong Won Kim, Jong Chol Kim
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Patent number: 10903214Abstract: The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.Type: GrantFiled: December 11, 2019Date of Patent: January 26, 2021Assignee: Renesas Electronics CorporationInventor: Takeshi Okagaki
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Patent number: 10796068Abstract: A standard cell design system is provided. The standard cell design system includes at least one processor configured to implement: a control engine that determines planar parameters and vertical parameters of a target standard cell, a three-dimensional structure generating engine that generates a three-dimensional structure of the target standard cell based on the planar parameters and the vertical parameters, an extraction engine that extracts a standard cell model of the target standard cell from the three-dimensional structure, an assessment engine that performs a plurality of assessment operations based on the standard cell model, and an auto-optimizing engine that adjusts, based on a machine learning algorithm, the planar parameters and the vertical parameters based on results of the plurality of assessment operations.Type: GrantFiled: April 22, 2019Date of Patent: October 6, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Uihui Kwon, Weiyi Qi, Yang Lu, Saetbyeol Ahn, Takeshi Okagaki
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Patent number: 10734374Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: GrantFiled: August 19, 2019Date of Patent: August 4, 2020Assignee: Renesas Electronics CorporationInventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
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Publication number: 20200119017Abstract: The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Bach of the first and the second inverters includes a p-channel transistor and art n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.Type: ApplicationFiled: December 11, 2019Publication date: April 16, 2020Inventor: Takeshi OKAGAKI
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Publication number: 20200082051Abstract: A standard cell design system is provided. The standard cell design system includes at least one processor configured to implement: a control engine that determines planar parameters and vertical parameters of a target standard cell, a three-dimensional structure generating engine that generates a three-dimensional structure of the target standard cell based on the planar parameters and the vertical parameters, an extraction engine that extracts a standard cell model of the target standard cell from the three-dimensional structure, an assessment engine that performs a plurality of assessment operations based on the standard cell model, and an auto-optimizing engine that adjusts, based on a machine learning algorithm, the planar parameters and the vertical parameters based on results of the plurality of assessment operations.Type: ApplicationFiled: April 22, 2019Publication date: March 12, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Uihui Kwon, Weiyi Qi, Yang Lu, Saetbyeol Ahn, Takeshi Okagaki
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Publication number: 20200066725Abstract: A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other, and having first side surfaces and second side surfaces opposing each other in a first direction, a gate electrode surrounding the channel layers and having a first end portion and a second end portion, opposing each other in the first direction, and a source/drain layer on a first side of the gate electrode and in contact with the channel layers, a portion of the source/drain layer protruding further than the first end portion of the gate electrode in the first direction, wherein a first distance from the first end portion of the gate electrode to the first side surfaces of the channel layers is shorter than a second distance from the second end portion of the gate electrode to the second side surfaces of the channel layers.Type: ApplicationFiled: March 20, 2019Publication date: February 27, 2020Inventors: Krishna Kumar BHUWALKA, Kyoung Min CHOI, Takeshi OKAGAKI, Dong Won KIM, Jong Chol KIM
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Patent number: 10541240Abstract: The semiconductor device includes a first inserter and a second inverter which is connected thereto in series. Each of the first and the second inserters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.Type: GrantFiled: January 7, 2019Date of Patent: January 21, 2020Assignee: Renesas Electronics CorporationInventor: Takeshi Okagaki
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Publication number: 20190378831Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: ApplicationFiled: August 19, 2019Publication date: December 12, 2019Applicant: Renesas Electronics CorporationInventors: Takeshi OKAGAKI, Koji SHIBUTANI, Makoto YABUUCHI, Nobuhiro TSUDA
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Patent number: 10490545Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: GrantFiled: August 6, 2018Date of Patent: November 26, 2019Assignee: Renesas Electronics CorporationInventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
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Patent number: 10396802Abstract: In order to provide a semiconductor device capable of detecting HCI degradation of a semiconductor element in a simple structure, the semiconductor device includes an oscillation circuit including a plurality of logic gates of various driving forces which are formed by transistors and coupled in series, a frequency counter that measures an oscillation frequency of the oscillation circuit, and a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value.Type: GrantFiled: June 10, 2016Date of Patent: August 27, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Mitsuhiko Igarashi, Kan Takeuchi, Takeshi Okagaki
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Patent number: 10361685Abstract: There is to provide a semiconductor device capable of predicting a wear-out failure based on the degradation stress cumulative amount of power supply voltage and environmental temperature imposed on the device, which includes a ring oscillator having a plurality of stages of inverters, and a control circuit that emphasizes the voltage dependency and temperature dependency of an oscillation frequency of the ring oscillator or a control circuit that emphasizes the temperature dependency not the voltage dependency.Type: GrantFiled: December 1, 2016Date of Patent: July 23, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kan Takeuchi, Masaki Shimada, Takeshi Okagaki, Yoshio Takazawa
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Publication number: 20190139958Abstract: The semiconductor device includes a first inserter and a second inverter which is connected thereto in series. Each of the first and the second inserters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of projection semiconductor layers each as the active region, of the channel and the n-channel transistors of the first inverter.Type: ApplicationFiled: January 7, 2019Publication date: May 9, 2019Inventor: Takeshi OKAGAKI
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Publication number: 20180350792Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.Type: ApplicationFiled: August 6, 2018Publication date: December 6, 2018Applicant: Renesas Electronics CorporationInventors: Takeshi OKAGAKI, Koji SHIBUTANI, Makoto YABUUCHI, Nobuhiro TSUDA
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Publication number: 20180254276Abstract: The semiconductor devise includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.Type: ApplicationFiled: May 7, 2018Publication date: September 6, 2018Inventor: Takeshi OKAGAKI