Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in off-state coupled in series, as a PUF element. The PUF element outputs a signal of high level or low level depending on the potential of a connection node of the first and the second MIS transistors. Preferably, the MIS transistors are fin-type FETs.

Abstract: The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.

Abstract: In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in off-state coupled in series, as a PUF element. The PUF element outputs a signal of high level or low level depending on the potential of a connection node of the first and the second MIS transistors. Preferably, the MIS transistors are fin-type FETs.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the channel and the n-channel transistors of the first inverter.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the transistors of the second inserter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.

Abstract: There is to provide a semiconductor device capable of predicting a wear-out failure based on the degradation stress cumulative amount of power supply voltage and environmental temperature imposed on the device, which includes a ring oscillator having a plurality of stages of inverters, and a control circuit that emphasizes the voltage dependency and temperature dependency of an oscillation frequency of the ring oscillator or a control circuit that emphasizes the temperature dependency not the voltage dependency.

Abstract: In order to realize a silicon PUF of lower power consumption, a semiconductor device includes first and second MIS transistors of the same conductive type in off-state coupled in series, as a PUF element. The PUF element outputs a signal of high level or low level depending on the potential of a connection node of the first and the second MIS transistors. Preferably, the MIS transistors are fin-type FETs.

Abstract: In order to provide a semiconductor device capable of detecting HCI degradation of a semiconductor element in a simple structure, the semiconductor device includes an oscillation circuit including a plurality of logic gates of various driving forces which are formed by transistors and coupled in series, a frequency counter that measures an oscillation frequency of the oscillation circuit, and a comparator that compares the oscillation frequency of the oscillation circuit measured by the frequency counter with a predetermined value.

Abstract: The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the transistors of the second inserter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: A capacitance measurement method is provided which is capable of measuring an accurate capacitance value even if a leakage current on a level that cannot be ignored occurs in a capacitance to be measured. In step S1, a test current ICnorm is measured by using a normal PMOS gate potential as a PMOS gate potential for providing on/off control of PMOS transistors in a predetermined cycle. In step S2, a current ICrat is measured by using, as the PMOS gate potential, a multiplied on-time PMOS gate potential, the “L” period and fall time of which are integral multiples of those of the normal PMOS gate potential. In step S3, based on the currents ICnorm, ICrat, a leakage current IRt is eliminated and the amount of capacity current CIC consisting only of a capacitance current component ICt is calculated. In step S5, a target capacitance is obtained based on the capacity current CIC and a charge frequency frat obtained in step S4.

Abstract: A capacitance measurement method is provided which is capable of measuring an accurate capacitance value even if a leakage current on a level that cannot be ignored occurs in a capacitance to be measured. In step S1, a test current ICnorm is measured by using a normal PMOS gate potential as a PMOS gate potential for providing on/off control of PMOS transistors in a predetermined cycle. In step S2, a current ICrat is measured by using, as the PMOS gate potential, a multiplied on-time PMOS gate potential, the “L” period and fall time of which are integral multiples of those of the normal PMOS gate potential. In step S3, based on the currents ICnorm, ICrat, a leakage current IRt is eliminated and the amount of capacity current CIC consisting only of a capacitance current component ICt is calculated. In step S5, a target capacitance is obtained based on the capacity current CIC and a charge frequency frat obtained in step S4.