Patents by Inventor Takeshi Onodera

Takeshi Onodera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5619157
    Abstract: A synchronizing circuit including a plurality of latches, comprised of a first dynamic type through latch circuit and a second dynamic type through latch circuit between which is disposed a static type through latch circuit, the circuits connected in cascade. Data is sampled at the timing of the rising edge of the clock signal generated by a pulse generation circuit connected to a clock input circuit and data is output at the timing of the trailing edge. By defining the clock pulse width generated at the pulse generation circuit larger than the clock skew, it is possible to prevent malfunctions of the LSI caused by clock skew caused by deviation of timing of the clock distribution. Moreover, by providing a dynamic type through circuit for a scan test input to the first dynamic type through latch circuit in parallel, a scanning function can be realized and a malfunction due to the clock skew during scanning can be prevented.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: April 8, 1997
    Assignee: Sony Corporation
    Inventors: Ichiro Kumata, Takeshi Onodera, Takenori Sugawara
  • Patent number: 5579322
    Abstract: An object of the present invention is to provide an embedded testing circuit of a dual port memory capable of effectively testing the memory using a short test pattern while making simultaneous write/read from both of the ports.The testing circuit comprises an address inputting circuit selectively supplying M-sequence pattern data or their inverted pattern data to scan registers on the port A at the address input side and also selectively supplying pattern data in inverse relationship to the pattern data supplied to the port A to scan registers on the port B and a data inputting circuit selectively supplying the M-sequence pattern data or their inverted pattern data passed through the scan registers on the port A at the address input side to scan registers on the port A at the data input side and also selectively supplying the inverted pattern data or the M-sequence pattern data passed through the scan registers on the port B at the address input side to scan registers on the port B at the data input side.
    Type: Grant
    Filed: August 25, 1994
    Date of Patent: November 26, 1996
    Assignee: Sony Corporation
    Inventor: Takeshi Onodera