Abstract: A memory card includes first and second interface units connected to a system host, a memory unit, and an additional information registration unit. The memory unit includes a first identifier storage unit that stores an identifier of the memory unit, a flash memory, and a memory controller that controls the first identifier storage unit and the flash memory via the first interface unit. The additional information registration unit includes a second identifier storage unit that stores an identifier same as the identifier of the memory unit, and an additional information notification unit that notifies the system host of the identifier in the second identifier storage unit and additional information via the second interface unit. When the memory card is connected to the system host, the memory unit and the additional information registration unit are associated with each other by the identifiers stored in the first and second identifier storage units.

Abstract: A data transfer system, which comprises a system host and an adaptor including a local host, is provided. The adaptor is connectable to a local device inserted into the adaptor and includes a switch unit configured to perform address translation and Requestor (Req) ID translation for data transfers between the local device and the system host. The system host checks, when the local device is inserted or removed while the system host is in operation, a type of a protocol applied to the local device and reloads a device driver based on a result of the check. The device driver includes a pre-sleep state storage configured to store an insertion and removal state of the local device immediately before the system host and the adaptor enter a sleep state.

Abstract: A recording control system includes a storage medium and a control device that is detachably connectable to and controls reading/writing of data to/from the storage medium. The storage medium stores a first authentication code corresponding to at least one first attribute of the storage medium among attributes regarding reading and writing. The control device includes: a readout unit that outputs first request information to the storage medium to read therefrom at least one common authentication code each corresponding to a respective one of at least one common attribute of the first authentication code and the first request information, the first request information corresponding to at least one second attribute of the control device; an identification unit that identifies the at least one common attribute according to the at least one common authentication code; and a control unit that controls the reading/writing according to the at least one common attribute.

Abstract: A memory card includes first and second interface units connected to a system host, a memory unit, and an additional information registration unit. The memory unit includes a first identifier storage unit that stores an identifier of the memory unit, a flash memory, and a memory controller that controls the first identifier storage unit and the flash memory via the first interface unit. The additional information registration unit includes a second identifier storage unit that stores an identifier same as the identifier of the memory unit, and an additional information notification unit that notifies the system host of the identifier in the second identifier storage unit and additional information via the second interface unit. When the memory card is connected to the system host, the memory unit and the additional information registration unit are associated with each other by the identifiers stored in the first and second identifier storage units.

Abstract: A memory device controlling apparatus of the present invention includes a device information requesting part that requests device information with respect to a memory device, when recognizing that the memory device is connected to the memory device controlling apparatus, and an extension activating part that activates an extension of the memory device based on the device information acquired in the device information requesting part. The memory device controlling apparatus accesses the memory device using the extension in the memory device. Such a configuration enables the memory device and the memory device controlling apparatus to be operated in an optimum operation mode in accordance with the characteristics of each bus, a host PC, and the memory device.

Abstract: System host (2) requests a command to local device (6), and local host (10) interprets the requested command and issues the command to local device (6). Local device (6) notifies local host (10) of an interrupt of command complete and local host (10) notifies system host (2) of the command complete. Data transfer between system host (2) and local device (6) is performed via advanced switching unit (8), and advanced switching unit (8) converts an address on local host (10) side into an address on system host (2) side and transfers PCI packets between local host (10) and system host (2).

Abstract: In cases where local devices (6, 6a) support a master transfer function, a portion of the memory space, of each of local devices (6, 6a), to be controlled from system host (2) is mapped onto a memory space on system host (2) side and a plurality of local devices (6, 6a) are reconfigured as one virtual local device. This provides information processing apparatus (4) which, in cases of connection with the plurality of local devices (6, 6a), resolves resource shortage on system host (2) side by appropriately mapping necessary registers of local devices (6, 6a) onto a memory space for system host (2).

Abstract: System host (2) requests a command to local device (6), and local host (10) interprets the requested command and issues the command to local device (6). Local device (6) notifies local host (10) of an interrupt of command complete and local host (10) notifies system host (2) of the command complete. Data transfer between system host (2) and local device (6) is performed via advanced switching unit (8), and advanced switching unit (8) converts an address on local host (10) side into an address on system host (2) side and transfers PCI packets between local host (10) and system host (2).

Abstract: In cases where local devices (6, 6a) support a master transfer function, a portion of the memory space, of each of local devices (6, 6a), to be controlled from system host (2) is mapped onto a memory space on system host (2) side and a plurality of local devices (6, 6a) are reconfigured as one virtual local device. This provides information processing apparatus (4) which, in cases of connection with the plurality of local devices (6, 6a), resolves resource shortage on system host (2) side by appropriately mapping necessary registers of local devices (6, 6a) onto a memory space for system host (2).

Abstract: According to one embodiment, a memory controller that writes write data provided from a host device into a memory, reads read data from the memory, and transmits the read data to the host device. The memory controller includes an external interface, a first ECC generating unit, an access unit, a first ECC correcting unit, and a control unit.

Abstract: A semiconductor recording apparatus includes a logical-to-physical conversion table 115 showing correspondence between a physical address of said semiconductor memory and a logical address and writes the table to a flash memory 120. On receiving a write command issued from a host device 200, a block management section 114 selects a physical block with reference to said logical-to-physical conversion table, and updates said logical-to-physical conversion table. A logical-to-physical conversion table initializing section 117 updates a physical address corresponding to each logical address of the logical-to-physical conversion table into an invalid address. Accordingly the apparatus can render the number of rewrites of physical blocks uniform irrespective of writing conditions.

Abstract: A command analyzer 160 determines whether or not a first write command after power-on is issued. A new block reserve determinator 170 determines that a new physical block is reserved, in a case where the command analyzer 160 determines that first writing command after power-on is issued and the physical block corresponding to a logical address at which a host device requests transmit is in a written state. At this time, the semiconductor memory device writes data to the new physical block. Thereby, data written before power disconnection does not been destroyed.

Abstract: An error correction code of (N+M) words is configured by adding an ECC parity of M word (M is a natural number) to N words extracted at an interval of A words with respect to data of (A*N) words (A and N are natural numbers) inputted via an interface. A data distributor distributes (N+M) words to the respective (N+M) physical blocks to record by A words. In a case where a writing error has occurred, data recorded in a cell sharing page of the page and in a page of another physical block configuring the error correction code is read. A disappearing correction is carried out to the data of the cell sharing page by using the data, and thus the data of the cell sharing page is recovered and written. In this manner, in the multi-level nonvolatile memory, an error in writing of a certain page can be prevented from propagating to a written page sharing a cell.

Abstract: User data transferred from a host apparatus and a first information table 35 indicating correspondence between a logical address and a physical address are recorded in a first region of a flash memory 20. A second information table 38 composed of the physical block address storing the first information table 35 and the number of times of update of the physical block for recording the first information table from the time of manufacturing is recorded in a second region of the flash memory 20. The physical blocks of the first and the second regions are recorded independently from each other in a rotational manner. According to the recording of the second information table, the total number of times of rewriting of the first region is converted. This can suppress the number of times of rewriting of the second region and improve reliability of the number of times of update of the first information table from the time of manufacturing, the number being recorded in the second region.

Abstract: A host device 200A includes a data buffer 250. When data has been already written to a part of a physical block and data is additionally written to the physical block, it is determined whether or not the data written to the physical block is held in the data buffer. When the data is held, data is written to the block, and when an error exists, data in unit of physical blocks is rewritten. When the data is not held in the data buffer, a new physical block is required to be secured and then, data is written to the new block. Thereby, even when power is shut off or an error occurs during writing in the semiconductor memory device, destruction of data already written is prevented.

Abstract: An error correction code of (N+M) words is configured by adding an ECC parity of M word (M is a natural number) to N words extracted at an interval of A words with respect to data of (A*N) words (A and N are natural numbers) inputted via an interface 1. A data distributor 3 distributes (N+M) words to the respective (N+M) physical blocks to record by A words. In a case where a writing error has occurred, data recorded in a cell sharing page of the page and in a page of another physical block configuring the error correction code is read. A disappearing correction is carried out to the data of the cell sharing page by using the data, and thus the data of the cell sharing page is recovered and written. In this manner, in the multi-level nonvolatile memory, an error in writing of a certain page can be prevented from propagating to a written page sharing a cell.

Abstract: A semiconductor recording apparatus includes a logical-to-physical conversion table 115 showing correspondence between a physical address of said semiconductor memory and a logical address and writes the table to a flash memory 120. On receiving a write command issued from a host device 200, a block management section 114 selects a physical block with reference to said logical-to-physical conversion table, and updates said logical-to-physical conversion table. A logical-to-physical conversion table initializing section 117 updates a physical address corresponding to each logical address of the logical-to-physical conversion table into an invalid address. Accordingly the apparatus can render the number of rewrites of physical blocks uniform irrespective of writing conditions.

Abstract: A host device 200A includes a data buffer 250. When data has been already written to a part of a physical block and data is additionally written to the physical block, it is determined whether or not the data written to the physical block is held in the data buffer. When the data is held, data is written to the block, and when an error exists, data in unit of physical blocks is rewritten. When the data is not held in the data buffer, a new physical block is required to be secured and then, data is written to the new block. Thereby, even when power is shut off or an error occurs during writing in the semiconductor memory device, destruction of data already written is prevented.

Abstract: A command analyzer 160 determines whether or not a first write command after power-on is issued. A new block reserve determinator 170 determines that a new physical block is reserved, in a case where the command analyzer 160 determines that first writing command after power-on is issued and the physical block corresponding to a logical address at which a host device requests transmit is in a written state. At this time, the semiconductor memory device writes data to the new physical block. Thereby, data written before power disconnection does not been destroyed.

Abstract: User data transferred from a host apparatus and a first information table 35 indicating correspondence between a logical address and a physical address are recorded in a first region of a flash memory 20. A second information table 38 composed of the physical block address storing the first information table 35 and the number of times of update of the physical block for recording the first information table from the time of manufacturing is recorded in a second region of the flash memory 20. The physical blocks of the first and the second regions are recorded independently from each other in a rotational manner. According to the recording of the second information table, the total number of times of rewriting of the first region is converted. This can suppress the number of times of rewriting of the second region and improve reliability of the number of times of update of the first information table from the time of manufacturing, the number being recorded in the second region.