Abstract: A memory card is equipped in a host apparatus and used for data recording. The memory card has a built-in flash memory and an internal ROM, there is prestored a predetermined writable block size corresponding to a certain integral multiple of a size of an erase block. A write block size of a write command issued by the host apparatus. The data size is detected and compared to the writable block size, so as to decide whether the write block size is an integral multiple of the writable block size, thereby judging whether write is permitted. Only when the write is permitted, data is written from the host apparatus into the memory card. If the write is not permitted, a response to inform an error is returned to the host apparatus.

Abstract: [OBJECT] To guarantee a data transfer rate irrespective of a performance of a memory card. [SOLVING MEANS] A parameter to show a data transfer efficiency is previously recorded in a recording medium 101 in which data is written per data size that can be increased and decreased stepwise and the data transfer efficiency is variable in accordance with the data size. Next, a data accessing apparatus 105 issues a parameter acquisition command to the recording medium 101. The recording medium 101 which received the parameter acquisition command transmits the parameter. The data accessing apparatus 105 collates the received parameter with the data transfer efficiency required in the data to be written/read to thereby select an optimum data size. Then, the data accessing apparatus 105 writes/reads the data to the recording medium 101 based on the selected optimum data size.

Abstract: A general purpose of the present invention is to stabilize a filter circuit to desired characteristics without increasing its circuit scale. An active filter unit includes a current control unit, a first gm-C filter unit, and a subsequent circuit. Using a signal output from a central control unit as an input, the current control unit outputs adjustment currents for adjusting gm values, corresponding to respective transconductance amplifiers, to the first gm-C filter unit. The subsequent circuit includes a load capacitance which is composed of an active element such as a transconductance amplifier. The first gm-C filter unit includes the plurality of transconductance amplifiers and a control unit which controls the gm values of the transconductance amplifiers. It limits the band of the signal output from a first filter signal selection unit, and outputs the result to the subsequent circuit.

Abstract: An analog-to-digital converter includes a track-and-hold circuit, a constant-voltage source, a threshold voltage selection circuit, a first comparator to a seventh comparator, an encoder, and a reference voltage output circuit. In a correction mode where the offsets of the first to seventh comparators are to be corrected, a track-and-hold circuit shuts off the input of an analog voltage to the first to seventh comparators by turning off the track-hold switch.

Abstract: A pressure sensor includes a sensor chip, a pressure receiving diaphragm, a connector case, and a case. A pressure sensing chamber is provide in the connector case and filled with oil. The sensor chip is arranged in the chamber and the diaphragm is fixed to the connector case such that it has contact with the oil and seals the chamber. An O-ring and a welding ring are placed around an edge of the diaphragm and the chamber between the diaphragm and the connector case. The diaphragm is fixed to the connector case via the O-ring and the welding ring and fixed. An inner portion of the welding ring is formed such that it can be placed between the sensor chip, wires, and the diaphragm in the chamber.

Abstract: The object is to provide a delay circuit capable of improving the accuracy of delay time with a simple circuit configuration. A delay circuit includes a first delay unit including a plurality of delay elements connected in series for detecting delay time characteristics of the first delay unit, a detection unit detects the number of delay elements used in the first delay unit to delay an input signal by a reference time, a second delay unit including a plurality of delay elements connected in series so as to output a signal delayed in accordance with the delay time characteristics of the first delay unit, and a selection unit selects the number of delay elements in the second delay unit to delay the input signal in accordance with the number of delay elements detected by the detection unit.

Abstract: An effective electronic settlement system in which the number of checks is small. The electronic settlement system includes a data storage device such as an IC card in which value information is stored, a client device provided with an information input/output function to the data storage device, a store device for providing commodities or services, a settlement management device for managing settlement between the data storage device and the store device, and a communication system for connecting the client device, the store device, and the settlement management device so as to enable bidirectional communication.

Abstract: An effective electronic settlement system in which the number of checks is small. The electronic settlement system includes a data storage device such as an IC card in which value information is stored, a client device provided with an information input/output function to the data storage device, a store device for providing commodities or services, a settlement management device for managing settlement between the data storage device and the store device, and a communication system for connecting the client device, the store device, and the settlement management device so as to enable bidirectional communication.

Abstract: A license management system includes a server for managing a plurality of kinds of accounts and issuance of a license key, and terminal apparatuses which access the server through a network by using respective predetermined accounts.

Abstract: A reproduced signal processor comprising sync block detecting means (100), data information generating means (106), first memory means (105), memory writing means (104), memory reading means (109) for parallel reading data of n frames (n is an integer of 2 or more satisfying ?<n) stored in the first memory means (105), and transferring means (112, 1504) for transferring n pieces of transfer data after restructuring n pieces of frame data read out by the memory reading means (109) according to the data information or not restructuring them.

Abstract: A pressure sensor includes a casing having a pressure detection chamber, a diaphragm for receiving pressure of a measuring object and disposed on the casing, and a pressure detection element. The pressure detection chamber is filled with a liquid, and the diaphragm contacts the liquid. The pressure detection element is disposed in the pressure detection chamber to receive the pressure of the liquid. The diaphragm has a plate shape with a radius of R and includes a circumference and a center of the plate. The circumference is fixed to the casing. The diaphragm further includes a corrugate disposed concentrically with the center of the diaphragm and having a half circular cross-section and a top of the half circle. The top of the corrugate is disposed within a distance of 0.6 R from the center of the diaphragm.

Abstract: A pressure sensor includes a sensor chip, a pressure receiving diaphragm, a connector case, and a case. A pressure sensing chamber is provide in the connector case and filled with oil. The sensor chip is arranged in the chamber and the diaphragm is fixed to the connector case such that it has contact with the oil and seals the chamber. An O-ring and a welding ring are placed around an edge of the diaphragm and the chamber between the diaphragm and the connector case. The diaphragm is fixed to the connector case via the O-ring and the welding ring and fixed. An inner portion of the welding ring is formed such that it can be placed between the sensor chip, wires, and the diaphragm in the chamber.

Abstract: A digital signal processing method comprising the steps of: (a) composing, a plurality of first encoded video data and a plurality of second encoded video data; (b) dividing, each of high quality M bits audio channel into audio data of upper L bits and audio data of lower M-L bits; (c) composing a plurality of first basic data and a plurality of second basic data, wherein each of the first basic data have respective audio data of upper “L” bits, and wherein the second basic data have respective audio data of audio data of lower “M-L”; and (d) transmitting the first basic data in a first data bus, and the second basic data in a second data bus.

Abstract: Pressure sensor includes a casing having a pressure detection chamber, a diaphragm for receiving pressure of a measuring object and disposed on the casing, and a pressure detection element. The pressure detection chamber is filled with a liquid, and the diaphragm contacts the liquid. The pressure detection element is disposed in the pressure detection chamber to receive the pressure of the liquid. The diaphragm has a plate shape with a radius of R and includes a circumference and a center of the plate. The circumference is fixed to the casing. The diaphragm further includes a corrugate disposed concentrically with the center of the diaphragm and having a half circular cross-section and a top of the half circle. The top of the corrugate is disposed within a distance of 0.6 R from the center of the diaphragm.

Abstract: A variable resistance circuit comprises a resistance circuit including a plurality of resistors serially connected, and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors. The bypass circuit includes a plurality of transistors selectively turned on or off. The variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed. The gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value. Various resistance values can be set in high precision by selectively turning on or off the plurality of transistors.

Abstract: Apparatus is adapted for recording and reproducing compressed video data in a selected one of two recording formats, of which a first format is for recording the compressed video data in N (N≧3, and representing an integer) number of tracks on a magnetic tape by dividing the video data into N number of groups, and a second format is for recording data, as auxiliary data independent from the compressed video data, in two of the tracks at both ends, and the compressed video data in (N−2) number of the tracks. In the second recording format, the recording is carried out by setting a data length of an error correction code for sync blocks longer than a data length of another error correction code for sync blocks in the first recording format.

Abstract: A variable resistance circuit comprises a resistance circuit including a plurality of resistors serially connected, and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors. The bypass circuit includes a plurality of transistors selectively turned on or off. The variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed. The gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value. Various resistance values can be set in high precision by selectively turning on or off the plurality of transistors.

Abstract: Eight resistors having resistance values of R×2i (i=0 to 7) (&OHgr;) are serially connected while eight switches exhibiting parasitic resistance values of r×2i (&OHgr;) in ON states are connected in parallel with the resistors respectively, for changing a resistance value by turning on/off the switches. The resistors are connected between an inversion input terminal of an operational amplifier and a terminal, and a non-inversion input terminal receives a prescribed reference voltage. Between the inversion input terminal and an output terminal of the operational amplifier, a resistor and a switch of a variable resistance circuit forming a negative feedback loop are connected to the output terminal while another resistor and another switch are connected to the inversion input terminal.

Abstract: A digital video cassette recorder reproduces signals which have been compressed to digital data and recorded in predetermined M tracks (M≧1) with helical scan in the unit of page consisting of N frames (N≧1). Further, position data have been added to the digital data on recording. On reproduction, the position data are detected to determine which reproduction position is reproduced, and a control signal to designate a field to be output is generated by observing the reproduction position during a frame period. A first storage device stores decoded data in the unit of N frames, while a second storage device delays the data a time of one field. By observing the reproduction situation with the position data, a memory controller controls reading from the first storage device according to the control signal, while a switch selects data to be output between data from the first storage device and data from the second storage device according to the control signal.