Abstract: Eight resistors having resistance values of R×2i (i=0 to 7) (&OHgr;) are serially connected while eight switches exhibiting parasitic resistance values of r×2i (&OHgr;) in ON states are connected in parallel with the resistors respectively, for changing a resistance value by turning on/off the switches. The resistors are connected between an inversion input terminal of an operational amplifier and a terminal, and a non-inversion input terminal receives a prescribed reference voltage. Between the inversion input terminal and an output terminal of the operational amplifier, a resistor and a switch of a variable resistance circuit forming a negative feedback loop are connected to the output terminal while another resistor and another switch are connected to the inversion input terminal.

Abstract: A comparator converts an input analog RF signal to a digital signal and inputs the digital signal in a charge pump circuit. The charge pump circuit controls charging/discharging of an integration capacitor in response to the output level of the digital signal output from the comparator. The charging quantity of the integration capacitor is used as a reference voltage of an RF amplifier, and a center voltage level of the analog RF signal output from the RF amplifier is adjusted in response to an average dc level of the digital signal. Thus, it follows that a slice level of a signal reproducing circuit is properly controlled.

Abstract: Eight resistors having resistance values of R×2i (i=0 to 7) (&OHgr;) are serially connected while eight switches exhibiting parasitic resistance values of r×2i (&OHgr;) in ON states are connected in parallel with the resistors respectively, for changing a resistance value by turning on/off the switches. The resistors are connected between an inversion input terminal of an operational amplifier and a terminal, and a non-inversion input terminal receives a prescribed reference voltage. Between the inversion input terminal and an output terminal of the operational amplifier, a resistor and a switch of a variable resistance circuit forming a negative feedback loop are connected to the output terminal while another resistor and another switch are connected to the inversion input terminal.

Abstract: An effective electronic settlement system in which the number of checks is small. The electronic settlement system includes a data storage device such as an IC card in which value information is stored, a client device provided with an information input/output function to the data storage device, a store device for providing commodities or services, a settlement management device for managing settlement between the data storage device and the store device, and a communication system for connecting the client device, the store device, and the settlement management device so as to enable bidirectional communication.

Abstract: Provided to a portable information terminal device (portable telephone set) (20), an information reading sensor (25) reads information stored in a chip memory (112) of an IC card (10) through an antenna coil (12) to store read information in a terminal memory (22) via a terminal CPU (21). Accordingly, by holding the IC card (10) with the information reading sensor (25), the information reading sensor (25) can read directory information. Responsive to operation of a keyboard (23), the terminal CPU (21) retrieves the stored information in the terminal memory (22) to obtain only desired information. In addition, the terminal CPU (21) displays retrieved information on a display portion (24).

Abstract: Apparatus is adapted for recording and reproducing compressed video data in a selected one of two recording formats, of which a first format is for recording the compressed video data in N (N≧3, and representing an integer) number of tracks on a magnetic tape by dividing the video data into N number of groups, and a second format is for recording data, as auxiliary data independent from the compressed video data, in two of the tracks at both ends, and the compressed video data in (N−2) number of the tracks. In the second recording format, the recording is carried out by setting a data length of an error correction code for sync blocks longer than a data length of another error correction code for sync blocks in the first recording format.

Abstract: Eight resistors having resistance values of R×2i (i=0 to 7) (&OHgr;) are serially connected while eight switches exhibiting parasitic resistance values of r×2i (&OHgr;) in ON states are connected in parallel with the resistors respectively, for changing a resistance value by turning on/off the switches. The resistors are connected between an inversion input terminal of an operational amplifier and a terminal, and a non-inversion input terminal receives a prescribed reference voltage. Between the inversion input terminal and an output terminal of the operational amplifier, a resistor and a switch of a variable resistance circuit forming a negative feedback loop are connected to the output terminal while another resistor and another switch are connected to the inversion input terminal.

Abstract: A digital signal processing method comprising the steps of:

Abstract: A digital image data processing apparatus has a preprocessing apparatus for preprocessing the digital video data before recording-and a post-processing apparatus for post-processing the digital video data after recording. The preprocessor receives a main channel signal and a sub channel signal, compresses these signals and concatenate into a single channel image data in which the signal position does not change each field for coding by a coder. Image deterioration during reproduction is prevented by a post-processor processing the image data decoded by a decoder by reversing the process applied by the preprocessor.

Abstract: A digital image data processing apparatus has a preprocessing apparatus for preprocessing the digital video data before recording and a post-processing apparatus for post-processing the digital video data after recording. The preprocessor receives a main channel signal and a sub channel signal, compresses these signals and concatenate into a single channel image data in which the signal position does not change each field for coding by a coder. Image deterioration during reproduction is prevented by a post-processor processing the image data decoded by a decoder by reversing the process applied by the preprocessor.