Patents by Inventor Takeshi Terasaki

Takeshi Terasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190287896
    Abstract: Provided is a semiconductor module enabling to effectively reduce, with a relatively simple structure, a thermal strain occurring in a bonding section between a semiconductor chip and other conductor members. The semiconductor module is characterized by being provided with: a first wiring layer; a semiconductor element bonded on the first wiring layer via a first bonding layer; a first electrode bonded on the semiconductor element via a second bonding layer; a second electrode connected on the first electrode; and a second wiring layer connected on the second electrode. The semiconductor module is also characterized in that: the width of the second electrode, said width being in the short-side direction, is more than the thickness of the first electrode; and the second electrode is disposed at a position off the center position of the semiconductor element.
    Type: Application
    Filed: March 17, 2017
    Publication date: September 19, 2019
    Inventors: Tomohisa SUZUKI, Takeshi TERASAKI
  • Publication number: 20190064790
    Abstract: This manufacturing facility management optimization device: on the basis of an operation condition of a manufacturing facility, creates, in a simulated manner in time series, an operation state which includes a measurement value, product yield, and quantities of raw materials consumed, of the manufacturing facility; detects an anomaly from the created operation state; identifies maintenance which corresponds to the detected anomaly, corrects the operation condition on the basis of the identified maintenance, and creates a plurality of post-correction operation condition candidates; creates, in a simulated manner in time series, a plurality of post-correction operation state candidates on the basis of the plurality of post-correction operation condition candidates; on the basis of the product yield and the quantities of raw materials consumed in the plurality of pre- and post-correction operation state candidates, and a unit price, creates a management index for the operation state and each of the plurality of
    Type: Application
    Filed: March 2, 2017
    Publication date: February 28, 2019
    Inventors: Hiroki YAMAMOTO, Masaaki MUKAIDE, Yoshinari HORI, Takeshi TERASAKI
  • Patent number: 9734931
    Abstract: It is an objective of the invention to provide a high-power supply cable characterized in that even when mounted in a narrow space where the cable undergoes a repetitive bending motion, any undesirable deformation out of the bending plane is small. There is provided a power-supply cable including: an electric wire including an electrical conductor and a resin sheath covering the electrical conductor, the electric wire having a tendency to generate a curl under a no-load condition, the curl having a curling direction, the curling direction being a normal to the curl, the electric wire having one or more longitudinal ends; a connecting terminal disposed at one of the longitudinal ends of the electric wire; and a curling tendency direction indicator showing the curling direction, the indicator being disposed along a normal line to the curl of the electric wire.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: August 15, 2017
    Assignee: HITACHI METALS, LTD.
    Inventors: Tomohisa Suzuki, Takeshi Terasaki, Fumihito Oka, Hirotaka Eshima, Naofumi Chiwata
  • Patent number: 9503018
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Publication number: 20160142011
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 19, 2016
    Inventors: Toshiaki TSUTSUMI, Yoshihiro FUNATO, Tomonori OKUDAIRA, Tadato YAMAGATA, Akihisa UCHIDA, Takeshi TERASAKI, Tomohisa SUZUKI, Yoshiharu KANEGAE
  • Patent number: 9252793
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: February 2, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Publication number: 20150083489
    Abstract: It is an objective of the invention to provide a high-power supply cable characterized in that even when mounted in a narrow space where the cable undergoes a repetitive bending motion, any undesirable deformation out of the bending plane is small. There is provided a power-supply cable including: an electric wire including an electrical conductor and a resin sheath covering the electrical conductor, the electric wire having a tendency to generate a curl under a no-load condition, the curl having a curling direction, the curling direction being a normal to the curl, the electric wire having one or more longitudinal ends; a connecting terminal disposed at one of the longitudinal ends of the electric wire; and a curling tendency direction indicator showing the curling direction, the indicator being disposed along a normal line to the curl of the electric wire.
    Type: Application
    Filed: August 19, 2014
    Publication date: March 26, 2015
    Inventors: Tomohisa SUZUKI, Takeshi TERASAKI, Fumihito OKA, Hirotaka ESHIMA, Naofumi CHIWATA
  • Publication number: 20150057987
    Abstract: An estimation apparatus executes an estimation method of out-of-plane deformation of a cable having a winding curl, the method including an input step of inputting parameters needed for the estimation; a step of deriving a value of an equivalent material property of the cable; a step of making a finite element analysis model reproducing the winding curl; a step of deforming the cable model to be in a straight state and calculating a stress distribution; a step of setting a rotational angle for determining an installation direction of the winding curl; a step of setting the calculated stress distribution and the set rotational angle to be initial states, deforming the straight cable model according to a load condition input at the input step, and calculating a deformation state and an amount of the out-of-plane deformation; and a step of outputting calculation results to an output device.
    Type: Application
    Filed: August 14, 2014
    Publication date: February 26, 2015
    Inventors: Tomohisa SUZUKI, Takeshi TERASAKI, Fumihito OKA, Hirotaka ESHIMA
  • Publication number: 20130314165
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Application
    Filed: November 29, 2010
    Publication date: November 28, 2013
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Patent number: 8319330
    Abstract: A semiconductor device having an improved whisker resistance in an exterior plating film is disclosed. The semiconductor device includes a tab with a semiconductor chip fixed thereto, plural inner leads, plural outer leads formed integrally with the inner leads, a plurality of wires for coupling electrode pads of the semiconductor chip and the inner leads with each other, and a sealing body for sealing the semiconductor chip. The outer leads project from the sealing body and an exterior plating film, which is a lead-free plating film, is formed on a surface of each of the outer leads.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: November 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Murakami, Takahiko Kato, Masato Nakamura, Takeshi Terasaki
  • Publication number: 20120012992
    Abstract: A semiconductor device having an improved whisker resistance in an exterior plating film is disclosed. The semiconductor device includes a tab with a semiconductor chip fixed thereto, plural inner leads, plural outer leads formed integrally with the inner leads, a plurality of wires for coupling electrode pads of the semiconductor chip and the inner leads with each other, and a sealing body for sealing the semiconductor chip. The outer leads project from the sealing body and an exterior plating film, which is a lead-free plating film, is formed on a surface of each of the outer leads.
    Type: Application
    Filed: July 13, 2011
    Publication date: January 19, 2012
    Inventors: Tomohiro MURAKAMI, Takahiko KATO, Masato NAKAMURA, Takeshi TERASAKI
  • Publication number: 20090108420
    Abstract: A technique capable of preventing whiskers which are generated in a plating film formed on the surface of each of leads of a semiconductor device is provided. Particularly, a technique capable of preventing generation of whiskers in a plating film containing tin as a primary material and not containing lead is provided. The plating film formed on the surface of the lead is formed so that a particular plane orientation among plane orientations of tin constituting the plating film is parallel to the surface of the lead. Specifically, the plating film is formed so that the (001) plane of tin is parallel to the surface of the lead. Thus, the coefficient of thermal expansion of tin constituting the plating film can be made to be lower than a coefficient of thermal expansion of the copper constituting the lead.
    Type: Application
    Filed: October 24, 2008
    Publication date: April 30, 2009
    Inventors: Yasutaka OKURA, Tomio IWASAKI, Takeshi TERASAKI
  • Patent number: 7298081
    Abstract: A display apparatus is disclosed with a vacuum seal member which has a shell structure. The display apparatus includes an anode substrate, a planar cathode substrate forming an electron emitting chamber vacuously sealed between the cathode substrate and the anode substrate, electron sources formed on the cathode substrate, phosphors formed on the anode substrate, and a vacuum seal member forming a pressure balancing chamber on the back of the electron emitting chamber side of the cathode substrate. The vacuum seal member is placed covering the back of the electron emitting chamber side, and has a shell structure for receiving the atmospheric pressure.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: November 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Terasaki, Atsushi Kazama, Makoto Kitano, Tatsuya Nagata, Takashi Fujimura
  • Publication number: 20070182023
    Abstract: By making coefficients of linear thermal expansion of stress relief members on upper and lower surface sides of a semiconductor chip small, thermal strain on joint members above and below the semiconductor chip is decreased and development of a crack therein is suppressed to ensure a joint area. Furthermore, by making areas of electrodes and stress relief members large enough to include a project plane of the semiconductor chip projected onto the joint surfaces thereof, even if a crack develops into the joint member between the stress relief member and the electrode, a joint area larger than the area of the semiconductor chip can be ensured for a certain amount of time. As a result, a semiconductor device capable of simultaneously ensuring the joint areas of the respective joint members and preventing a decrease in heat release capability is provided.
    Type: Application
    Filed: January 16, 2007
    Publication date: August 9, 2007
    Applicant: Hitachi, Ltd.
    Inventors: Shinji Hiramitsu, Satoshi Matsuyoshi, Koji Sasaki, Takeshi Terasaki
  • Publication number: 20050258735
    Abstract: An object of the present invention is to achieve high resolution, lightening, and thinning of a display apparatus. The display apparatus includes an anode substrate, a planar cathode substrate forming an electron emitting chamber vacuously sealed between the cathode substrate and the anode substrate, electron sources formed on the cathode substrate, phosphors formed on the anode substrate, and a vacuum seal member forming a pressure balancing chamber on the back of the electron emitting chamber side of the cathode substrate. The vacuum seal member is placed covering the back of the electron emitting chamber side, and has a shell structure for receiving the atmospheric pressure.
    Type: Application
    Filed: May 19, 2005
    Publication date: November 24, 2005
    Inventors: Takeshi Terasaki, Atsushi Kazama, Makoto Kitano, Tatsuya Nagata, Takashi Fujimura
  • Publication number: 20050258736
    Abstract: To achieve high resolution, lightening, and thinning in a display apparatus, the display apparatus includes a thin display panel and a control unit. The display panel includes an anode substrate, a cathode substrate forming an electron emitting chamber vacuously sealed between itself and the anode substrate, phosphors formed on the anode substrate, and a pressure support formed on the back of the electron emitting chamber side of the cathode substrate. The pressure support includes a vacuum seal member forming a pressure supporting chamber vacuously sealed between itself and the cathode substrate independently of the electron emitting chamber, and a reinforcement member which is formed of a member having a gap, which is sandwiched between the vacuum seal member and cathode substrate in the pressure supporting member, and at least both end portions of which span a bonding area of the cathode substrate for the anode substrate.
    Type: Application
    Filed: May 20, 2005
    Publication date: November 24, 2005
    Inventors: Atsushi Kazama, Takeshi Terasaki, Makoto Kitano, Tatsuya Nagata, Takashi Fujimura
  • Patent number: 6844219
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: January 18, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
  • Patent number: 6465876
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bond ed to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
  • Publication number: 20020011661
    Abstract: A semiconductor chip has a semiconductor chip, a support electrode body bonded to one of the end portions of the semiconductor chip and supported by, and fixed to, a heat spreader at a support fixing portion thereof, a lead electrode body bonded to the other end portion of the semiconductor chip and an insulating/sealing member disposed at the bond portion between the semiconductor chip and the support electrode body and at the bond portion between the semiconductor chip and the lead electrode body. The support electrode body includes a portion having an outer diameter different from that of the support fixing portion at which the support electrode body is supported and fixed by the heat spreader.
    Type: Application
    Filed: April 3, 2001
    Publication date: January 31, 2002
    Inventors: Takeshi Terasaki, Hideo Miura, Chikara Nakajima, Makoto Kitano
  • Patent number: 6331730
    Abstract: A push-in type semiconductor chip has a semiconductor device, a support electrode body bonded to one of the end portions of the semiconductor chip and supported by, and fixed to, a heat spreader at a support fixing portion thereof, a lead electrode body bonded to the other end portion of the semiconductor chip and an insulating/sealing member disposed at the bond portion between the semiconductor chip and the support electrode body and at the bond portion between the semiconductor chip and the lead electrode body. The support electrode body includes a first portion having an outer diameter different from that of the support fixing portion at which the support electrode body is supported and fixed by the heat spreader. By setting a predetermined relationship between the outer diameters of the first portion and the support fixing portion, deformation and breakage of the semiconductor chip during assembly can be prevented.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: December 18, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Terasaki, Hideo Miura, Chikara Nakajima, Makoto Kitano