Patents by Inventor Takeshi Toda
Takeshi Toda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12246196Abstract: Provided are novel antibody-pyrrolodiazepine derivative and novel antibody-pyrrolodiazepine derivative conjugates, as well as methods of using the same, and a novel CLDN6 and/or CLDN9 antibody. The disclosed compounds are of the class of alkyl benzene sulfonyl ureas, useful as oral anti-diabetics, and include substituted benzo[e]pyrrolo[1,2-?][1,4]diazepine.Type: GrantFiled: June 26, 2022Date of Patent: March 11, 2025Assignee: DAIICHI SANKYO COMPANY, LIMITEDInventors: Narihiro Toda, Yusuke Ota, Fuminao Doi, Masaki Meguro, Ichiro Hayakawa, Shinji Ashida, Takeshi Masuda, Takashi Nakada, Mitsuhiro Iwamoto, Naoya Harada, Tomoko Terauchi, Daisuke Okajima, Kensuke Nakamura, Hiroaki Uchida, Hirofumi Hamada
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Patent number: 12250813Abstract: According to the present embodiment, a semiconductor device includes a semiconductor substrate, a memory transistor, and a MOS transistor. The memory transistor includes at least a first silicon dioxide film and a first gate electrode positioned on the semiconductor substrate in order. The MOS transistor includes a second silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order. Any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the memory transistor.Type: GrantFiled: August 7, 2023Date of Patent: March 11, 2025Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Yu Nakane, Nobuyuki Toda, Hiroyoshi Kitahara, Takeshi Yamamoto, Naozumi Terada
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Patent number: 12242952Abstract: According to one embodiment, in nth (n is a natural number) processing, a first node calculates a first gradient to update a first weight and a second node calculates a second gradient to update the first weight. In mth (m is a natural number) processing, a third node calculates a third gradient to update a third weight and a fourth node calculates a fourth gradient to update the third weight. If the calculation by the first and second nodes is faster than the calculation by the third and fourth nodes, in n+1th processing, a second weight updated from the first weight is further updated using the first and second gradients, and, in m+1th processing, a fourth weight updated from the third weight is further updated using the first to fourth gradients.Type: GrantFiled: September 12, 2018Date of Patent: March 4, 2025Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Toda, Kosuke Haruki
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Patent number: 12188795Abstract: A main object of the present disclosure is to provide a reflection-type optical encoder scale capable of sufficiently reducing the reflectance on a low reflection region. The present disclosure achieves the object by providing a reflection-type optical encoder scale comprising a high reflection region and a low reflection region alternately placed on a substrate, wherein the low reflection region includes a low reflection portion including a metallic chromium film formed on the substrate, and a chromium oxide film and a chromium nitride film randomly formed on the metallic chromium film; and the high reflection region has higher reflectance of incident light from opposite side to the substrate of the reflection-type optical encoder scale, than the low reflection region.Type: GrantFiled: March 30, 2021Date of Patent: January 7, 2025Assignee: Dai Nippon Printing Co., Ltd.Inventors: Shinsuke Nakazawa, Takeshi Toda, Naoya Oda
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Publication number: 20240393143Abstract: A main object of the present disclosure is to provide a reflection-type optical encoder scale capable of sufficiently reducing the reflectance on a low reflection region. The present disclosure achieves the object by providing a reflection-type optical encoder scale comprising: a high reflection region and a low reflection region alternately placed on a transparent substrate, wherein the low reflection region includes a low reflection portion including at least three stacked inorganic layers, and a reflectance on the low reflection region is 5% or less, wherein the high reflection region includes at least one stacked inorganic layer, and a reflectance on the high reflection region is 60% or more, and wherein a value of a ratio S/N represented by the following formula (3) is 6 or more, (3) the ratio S/N=the reflectance on the high reflection region/the reflectance on the low reflection region.Type: ApplicationFiled: August 6, 2024Publication date: November 28, 2024Applicant: Dai Nippon Printing Co., Ltd.Inventors: Shinsuke NAKAZAWA, Takeshi TODA, Naoya ODA
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Publication number: 20230126475Abstract: A main object of the present disclosure is to provide a reflection-type optical encoder scale capable of sufficiently reducing the reflectance on a low reflection region. The present disclosure achieves the object by providing a reflection-type optical encoder scale comprising a high reflection region and a low reflection region alternately placed on a substrate, wherein the low reflection region includes a low reflection portion including a metallic chromium film formed on the substrate, and a chromium oxide film and a chromium nitride film randomly formed on the metallic chromium film; and the high reflection region has higher reflectance of incident light from opposite side to the substrate of the reflection-type optical encoder scale, than the low reflection region.Type: ApplicationFiled: March 30, 2021Publication date: April 27, 2023Applicant: Dai Nippon Printing Co., Ltd.Inventors: Shinsuke NAKAZAWA, Takeshi TODA, Naoya ODA
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Patent number: 11526690Abstract: A learning device includes one or more processors. The processors generate a plurality of pieces of learning data to be used in a plurality of learning processes, respectively, to learn a parameter of a neural network using an objective function. The processors calculate a first partial gradient using a partial data and the parameter added with noise, with respect to at least a part of the learning data out of the plurality of pieces of learning data. The partial data is obtained by dividing the learning data. The first partial gradient is a gradient of the objective function relating to the parameter for the partial data. The noise is calculated based on a second partial gradient calculated for another piece of the learning data. The processors update the parameter using the first partial gradient.Type: GrantFiled: August 28, 2019Date of Patent: December 13, 2022Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Toda, Kosuke Haruki
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Publication number: 20200234082Abstract: A learning device includes one or more processors. The processors generate a plurality of pieces of learning data to be used in a plurality of learning processes, respectively, to learn a parameter of a neural network using an objective function. The processors calculate a first partial gradient using a partial data and the parameter added with noise, with respect to at least a part of the learning data out of the plurality of pieces of learning data. The partial data is obtained by dividing the learning data. The first partial gradient is a gradient of the objective function relating to the parameter for the partial data. The noise is calculated based on a second partial gradient calculated for another piece of the learning data. The processors update the parameter using the first partial gradient.Type: ApplicationFiled: August 28, 2019Publication date: July 23, 2020Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi TODA, Kosuke HARUKI
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Patent number: 10661701Abstract: A blade receives light emitted from a light source and repeats a predetermined periodic motion to scan the front of a vehicle with reflected light of the emitted light. A position detector generates a position detection signal S4 indicating a timing at which a predetermined reference point of the blade passes a predetermined position. Based on the position detection signal S4, a period calculator calculates a period Tp of the periodic motion of the blade. A light intensity calculator receives light-distribution-pattern information S3 to be formed in front of the vehicle and calculates light intensity to be generated by the light source at each time based on the position detection signal S4 and the period Tp. A driver turns on a semiconductor light source so as to obtain the light intensity calculated by the light intensity calculator at each time.Type: GrantFiled: June 22, 2017Date of Patent: May 26, 2020Assignee: KOITO MANUFACTURING CO., LTD.Inventors: Takeshi Toda, Kentarou Murakami, Masayasu Ito, Takao Muramatsu, Hidetada Tanaka, Satoshi Yamamura
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Patent number: 10609774Abstract: A lighting circuit includes a voltage converter configured to receive a DC voltage to perform voltage conversion and supply a drive current to a light source unit including a light emitting element, a bypass switch configured to form a bypass path through which the drive current bypasses the light emitting element, and a controller configured to control the voltage converter and the bypass switch. The light source unit includes a plurality of light emitting elements connected in series. The bypass path includes at least one bypass switch which are connected in parallel with at least one of the light emitting elements. When turning on the light emitting element of the light source unit, the controller controls the voltage conversion to start in a state where the bypass switch is turned on, and then, turns off the bypass switch to turn on the light emitting element.Type: GrantFiled: July 1, 2016Date of Patent: March 31, 2020Assignee: KIOTO MANUFACTURING CO., LTD.Inventors: Toshiyuki Tsuchiya, Takao Muramatsu, Takeshi Toda
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Publication number: 20190188563Abstract: According to one embodiment, in nth (n is a natural number) processing, a first node calculates a first gradient to update a first weight and a second node calculates a second gradient to update the first weight. In mth (m is a natural number) processing, a third node calculates a third gradient to update a third weight and a fourth node calculates a fourth gradient to update the third weight. If the calculation by the first and second nodes is faster than the calculation by the third and fourth nodes, in n+1th processing, a second weight updated from the first weight is further updated using the first and second gradients, and, in m+1th processing, a fourth weight updated from the third weight is further updated using the first to fourth gradients.Type: ApplicationFiled: September 12, 2018Publication date: June 20, 2019Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi TODA, Kosuke HARUKI
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Publication number: 20190008010Abstract: A lighting circuit includes a voltage converter configured to receive a DC voltage to perform voltage conversion and supply a drive current to a light source unit including a light emitting element, a bypass switch configured to form a bypass path through which the drive current bypasses the light emitting element, and a controller configured to control the voltage converter and the bypass switch. The light source unit includes a plurality of light emitting elements connected in series. The bypass path includes at least one bypass switch which are connected in parallel with at least one of the light emitting elements. When turning on the light emitting element of the light source unit, the controller controls the voltage conversion to start in a state where the bypass switch is turned on, and then, turns off the bypass switch to turn on the light emitting element.Type: ApplicationFiled: July 1, 2016Publication date: January 3, 2019Applicants: KOITO MANUFACTURING CO., LTD., KOITO MANUFACTURING CO., LTD.Inventors: Toshiyuki Tsuchiya, Takao Muramatsu, Takeshi Toda
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Publication number: 20170282786Abstract: A blade receives light emitted from a light source and repeats a predetermined periodic motion to scan the front of a vehicle with reflected light of the emitted light. A position detector generates a position detection signal S4 indicating a timing at which a predetermined reference point of the blade passes a predetermined position. Based on the position detection signal S4, a period calculator calculates a period Tp of the periodic motion of the blade. A light intensity calculator receives light-distribution-pattern information S3 to be formed in front of the vehicle and calculates light intensity to be generated by the light source at each time based on the position detection signal S4 and the period Tp. A driver turns on a semiconductor light source so as to obtain the light intensity calculated by the light intensity calculator at each time.Type: ApplicationFiled: June 22, 2017Publication date: October 5, 2017Applicant: Koito Manufacturing Co., Ltd.Inventors: Takeshi TODA, Kentarou MURAKAMI, Masayasu ITO, Takao MURAMATSU, Hidetada TANAKA, Satoshi YAMAMURA
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Patent number: 9450089Abstract: A decrease in resistance against an abnormal current of a semiconductor device is suppressed. A first transistor is sandwiched between two second transistors (a first one and a second one of the second transistors) in a second direction. Both of a distance between a second source contact and a second drain contact that are coupled to the one second transistor, and a distance between a second source contact and a second drain contact that are coupled to the other second transistor are larger than a distance between a second source contact and a second drain contact that are coupled to a third one of the second transistors located farthest from the first transistor in the second direction.Type: GrantFiled: January 27, 2015Date of Patent: September 20, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takeshi Toda, Mototsugu Okushima
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Publication number: 20150214359Abstract: A decrease in resistance against an abnormal current of a semiconductor device is suppressed. A first transistor is sandwiched between two second transistors (a first one and a second one of the second transistors) in a second direction. Both of a distance between a second source contact and a second drain contact that are coupled to the one second transistor, and a distance between a second source contact and a second drain contact that are coupled to the other second transistor are larger than a distance between a second source contact and a second drain contact that are coupled to a third one of the second transistors located farthest from the first transistor in the second direction.Type: ApplicationFiled: January 27, 2015Publication date: July 30, 2015Inventors: Takeshi Toda, Mototsugu Okushima
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Publication number: 20140319591Abstract: In an interlayer insulating film in which contact plugs are embedded, a capacitor element is formed which has electrodes each formed of a metal. Over a substrate, the interlayer insulating film is formed. The interlayer insulating film includes a first insulating film and a second insulating film. In the second insulating film, the first and second contact plugs are formed. The first and second contact plugs extend through the second insulating film to reach first and second gate electrodes. In a surface of the substrate, an isolation film is formed. Within a region overlapping the isolation film in planar view, the capacitor element is formed. The capacitor element includes the lower and upper electrodes. Each of the lower and upper electrodes contains a metal. The lower and upper electrodes of the capacitor element are formed over the first insulating film to be embedded in the second insulating film.Type: ApplicationFiled: April 14, 2014Publication date: October 30, 2014Applicant: Renesas Electronics CorporationInventor: Takeshi TODA
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Patent number: 8803285Abstract: A semiconductor device has a capacitive structure formed by sequentially layering, on a wiring or conductive plug, a lower electrode, a capacitive insulation film, and an upper electrode. The semiconductor device has, as the capacitive structure, a thin-film capacitor having a lower electrode structure composed of an amorphous or microcrystalline film or a laminate of these films formed on a polycrystalline film.Type: GrantFiled: May 8, 2007Date of Patent: August 12, 2014Assignee: Renesas Electronics CorporationInventors: Hiroto Ohtake, Naoya Inoue, Ippei Kume, Takeshi Toda, Yoshihiro Hayashi
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Patent number: 8743836Abstract: Provided is a radio communication method employed in a base station having plural antenna elements. The method includes the steps of: setting an inner zone and an outer zone by dividing a cell formed by the base station into two; determining whether a mobile station is located in the inner zone or the outer zone on the basis of a predetermined criterion; notifying the mobile station located in the inner zone of control information, including information on channel allocation and a communication method, through a broadcast channel; and notifying the mobile station located in the outer zone of control information through a dedicated channel by beamforming using the plural antenna elements.Type: GrantFiled: October 23, 2007Date of Patent: June 3, 2014Assignee: Kyocera CorporationInventors: Takeshi Toda, Shingo Joko, Taku Nakayama, Kenta Okino
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Patent number: 8565826Abstract: A radio base station 100 includes fading rate measurement units 103a to 103n configured to measure a fading rate of a radio signal for each of the antenna elements 101a to 101n, the radio signal being received through the antenna elements; and a reference signal calculator 105 configured to output a reference signal used in an adaptive control of the directivity of the array antenna 101. The reference signal calculator 105 outputs the reference signal on the basis of a plurality of fading rates measured by the fading rate measurement units 103a to 103n.Type: GrantFiled: April 25, 2008Date of Patent: October 22, 2013Assignee: Kyocera CorporationInventors: Kenta Okino, Takeshi Toda, Chiharu Yamazaki
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Patent number: 8481399Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film above a semiconductor substrate, forming a wiring to be buried in the first insulating film, forming a protruding portion in an upper surface of the wiring, forming a second insulating film above the first insulating film and the wiring including the protruding portion, planarizing a surface of the second insulating film, forming a third insulating film on the second insulating film whose surface is planarized, forming a lower electrode on the third insulating film, forming a capacitor insulating film on the lower electrode, and forming an upper electrode on the capacitor insulating film.Type: GrantFiled: September 24, 2011Date of Patent: July 9, 2013Assignee: Renesas Electronics CorporationInventors: Masayuki Furumiya, Takeshi Toda