Patents by Inventor Takeshi Tokuyama
Takeshi Tokuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110299265Abstract: A power module and a power converter device including the power module include: two base plates with their main surfaces facing each other; a semiconductor circuit unit disposed between the two base plates; a connecting member that is connected to the two base plates and forms a housing region in which the semiconductor circuit unit is housed; and an insulating member that is placed between the base plate and the semiconductor circuit unit and secures electrical insulation of the base plate and the semiconductor circuit unit. A rigidity or thickness of the connecting member is less than a rigidity or thickness of the base plate.Type: ApplicationFiled: October 30, 2009Publication date: December 8, 2011Inventors: Kinya Nakatsu, Hiroshi Hozoji, Takeshi Tokuyama, Yusuke Takagi, Toshiya Satoh, Taku Oyama, Takanori Ninomiya
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Patent number: 8064234Abstract: Technology leading to a size reduction in a power conversion apparatus comprising a cooling function and technology relating to enhancing productivity and enhancing reliability necessary for commercial production are provided. Series circuits comprising an upper arm and lower arm of an inverter circuit are built in a single semiconductor module 500. The semiconductor module has cooling metal on two sides. An upper arm semiconductor chip and lower arm semiconductor chip are wedged between the cooling metals. The semiconductor module is inserted inside a channel case main unit 214. A DC positive electrode terminal 532, a DC negative electrode terminal 572, and an alternating current terminal 582 of a semiconductor chip are disposed in the semiconductor module. The DC terminals 532 and 572 are electrically connected with a terminal of a capacitor module. The alternating current terminal 582 is electrically connected with a motor generator via an AC connector.Type: GrantFiled: January 25, 2008Date of Patent: November 22, 2011Assignee: Hitachi, Ltd.Inventors: Takeshi Tokuyama, Kinya Nakatsu, Ryuichi Saito
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Publication number: 20110228479Abstract: An electric power conversion apparatus includes: a channel case in which a cooling water channel is formed; a double side cooling semiconductor module that comprises an upper and lower arms series circuit of an inverter circuit; a capacitor module; a direct current connector; and an alternate current connector. The semiconductor module comprises a first and a second heat dissipation metals whose outer surfaces are heat dissipation surfaces, the upper and lower arms series circuit is disposed tightly between the first heat dissipation metal and the second heat dissipation metal, and the semiconductor module further comprises a direct current positive terminal, a direct current negative terminal, and an alternate current terminal which protrude to outside. The channel case is provided with the cooling water channel which extends from a cooling water inlet to a cooling water outlet, and a first opening which opens into the cooling water channel.Type: ApplicationFiled: June 3, 2011Publication date: September 22, 2011Applicant: Hitachi, Ltd.Inventors: Takeshi TOKUYAMA, Kinya NAKATSU, Ryuichi SAITO, Keisuke HORIUCHI, Toshiya SATOH, Hideki MIYAZAKI
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Patent number: 7978471Abstract: An electric power conversion apparatus includes: a channel case in which a cooling water channel is formed; a double side cooling semiconductor module that comprises an upper and lower arms series circuit of an inverter circuit; a capacitor module; a direct current connector; and an alternate current connector. The semiconductor module comprises a first and a second heat dissipation metals whose outer surfaces are heat dissipation surfaces, the upper and lower arms series circuit is disposed tightly between the first heat dissipation metal and the second heat dissipation metal, and the semiconductor module further comprises a direct current positive terminal, a direct current negative terminal, and an alternate current terminal which protrude to outside. The channel case is provided with the cooling water channel which extends from a cooling water inlet to a cooling water outlet, and a first opening which opens into the cooling water channel.Type: GrantFiled: February 19, 2009Date of Patent: July 12, 2011Assignee: Hitachi, Ltd.Inventors: Takeshi Tokuyama, Kinya Nakatsu, Ryuichi Saito, Keisuke Horiuchi, Toshiya Satoh, Hideki Miyazaki
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Patent number: 7968925Abstract: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.Type: GrantFiled: September 21, 2010Date of Patent: June 28, 2011Assignee: Hitachi, Ltd.Inventors: Takeshi Tokuyama, Kinya Nakatsu, Ryuichi Saito
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Patent number: 7961472Abstract: The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces.Type: GrantFiled: April 26, 2007Date of Patent: June 14, 2011Assignee: Hitachi, Ltd.Inventors: Takeshi Tokuyama, Kinya Nakatsu, Atsushi Kawabata
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Publication number: 20110069455Abstract: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.Type: ApplicationFiled: September 21, 2010Publication date: March 24, 2011Applicant: Hitachi, Ltd.Inventors: Takeshi TOKUYAMA, Kinya Nakatsu, Ryuichi Saito
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Patent number: 7812443Abstract: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.Type: GrantFiled: April 1, 2008Date of Patent: October 12, 2010Assignee: Hitachi, Ltd.Inventors: Takeshi Tokuyama, Kinya Nakatsu, Ryuichi Saito
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Publication number: 20100165577Abstract: The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces.Type: ApplicationFiled: March 1, 2010Publication date: July 1, 2010Applicant: Hitachi, Ltd.Inventors: Takeshi TOKUYAMA, Kinya Nakatsu, Atushi Kawabata
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Publication number: 20090231811Abstract: An electric power conversion apparatus includes: a channel case in which a cooling water channel is formed; a double side cooling semiconductor module that comprises an upper and lower arms series circuit of an inverter circuit; a capacitor module; a direct current connector; and an alternate current connector. The semiconductor module comprises a first and a second heat dissipation metals whose outer surfaces are heat dissipation surfaces, the upper and lower arms series circuit is disposed tightly between the first heat dissipation metal and the second heat dissipation metal, and the semiconductor module further comprises a direct current positive terminal, a direct current negative terminal, and an alternate current terminal which protrude to outside. The channel case is provided with the cooling water channel which extends from a cooling water inlet to a cooling water outlet, and a first opening which opens into the cooling water channel.Type: ApplicationFiled: February 19, 2009Publication date: September 17, 2009Applicant: Hitachi. Ltd.Inventors: Takeshi Tokuyama, Kinya Nakatsu, Ryuichi Saito, Keisuke Horiuchi, Toshiya Satoh, Hideki Miyazaki
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Publication number: 20080251909Abstract: A double-face-cooled semiconductor module with an upper arm and a lower arm of an inverter circuit includes first and second heat dissipation members, each having a heat dissipation surface on one side and a conducting member formed on another side through an insulation member. On the conducting member on the first dissipation plate is provided with a fixing portion that fixes a collector surface of the semiconductor chip and a gate conductor connected to a gate terminal of the semiconductor module. The gate electrode terminal and the gate conductor are wire bonded. The conducting member on the second heat dissipation member is connected to an emitter surface of the semiconductor chip connected to the first heat dissipation member. The productivity and reliability are improved by most of formation operations for the upper and lower arms series circuit on one of the heat dissipation member.Type: ApplicationFiled: April 1, 2008Publication date: October 16, 2008Applicant: Hitachi, Ltd.Inventors: Takeshi TOKUYAMA, Kinya NAKATSU, Ryuichi SAITO
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Publication number: 20080186751Abstract: Technology leading to a size reduction in a power conversion apparatus comprising a cooling function and technology relating to enhancing productivity and enhancing reliability necessary for commercial production are provided. Series circuits comprising an upper arm and lower arm of an inverter circuit are built in a single semiconductor module 500. The semiconductor module has cooling metal on two sides. An upper arm semiconductor chip and lower arm semiconductor chip are wedged between the cooling metals. The semiconductor module is inserted inside a channel case main unit 214. A DC positive electrode terminal 532, a DC negative electrode terminal 572, and an alternating current terminal 582 of a semiconductor chip are disposed in the semiconductor module. The DC terminals 532 and 572 are electrically connected with a terminal of a capacitor module. The alternating current terminal 582 is electrically connected with a motor generator via an AC connector.Type: ApplicationFiled: January 25, 2008Publication date: August 7, 2008Inventors: Takeshi TOKUYAMA, Kinya Nakatsu, Ryuichi Saito
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Publication number: 20070252169Abstract: The present invention provides an electric circuit device in which it is possible to achieve simultaneously the improvement of cooling performance and reduction in operating loss due to line inductance. The above object can be attained by constructing multiple plate-like conductors so that each of these conductors electrically connected to multiple semiconductor chips is also thermally connected to both chip surfaces of each such semiconductor chip to release heat from the chip surfaces of each semiconductor chip, and so that among the above conductors, a DC positive-polarity plate-like conductor and a DC negative-polarity plate-like conductor are opposed to each other at the respective conductor surfaces.Type: ApplicationFiled: April 26, 2007Publication date: November 1, 2007Applicant: Hitachi, Ltd.Inventors: Takeshi Tokuyama, Kinya Nakatsu, Atushi Kawabata
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Patent number: 6492593Abstract: A gold wire, for semiconductor element connection, having 5-100 ppm by weight of Ca, 5-100 ppm by weight of Gd, and 1-100 ppm by weight of Y. The gold wire further preferably has 1-100 ppm by weight of at least one of Eu, La, Ce and Lu, as well as 1-100 ppm by weight of at least one of Mg and Ti. The total amount of the added elements being no greater than 200 ppm by weight. The balance being gold and unavoidable impurities. A semiconductor element connection method by ball bonding or bump connection using the gold wire.Type: GrantFiled: May 31, 2001Date of Patent: December 10, 2002Assignee: Tanaka Denshi Kogyo K.K.Inventors: Hiroshi Murai, Shuichi Mitoma, Takeshi Tokuyama, Mitutomo Motomura
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Publication number: 20020007957Abstract: A gold wire, for semiconductor element connection, consisting of 5-100 ppm by weight of Ca, 5-100 ppm by weight of Gd, 1-100 ppm by weight of Y and preferably 1-100 ppm by weight of at least one from among rare earth elements other than Y, as well as 1-100 ppm by weight of at least one from among Mg, Ti and Pb, the total amount of these elements being no greater than 200 ppm by weight, the balance being gold and unavoidable impurities. A semiconductor element connection method by ball bonding or bump connection using the gold wire.Type: ApplicationFiled: May 31, 2001Publication date: January 24, 2002Inventors: Hiroshi Murai, Shuichi Mitoma, Takeshi Tokuyama, Mitutomo Motomura
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Method and apparatus for deriving association rules from data and for segmenting rectilinear regions
Patent number: 5991752Abstract: The present application discloses a method and apparatus for extracting association rules from data having two or more numeric attributes and a true-false attribute, and for presenting the rules in an easily understandable form. The method comprises the steps of: (i) storing numbers u(i,j) and v(i,j) of data in each pixel whose true-false attribute is true, so as to correspond to each pixel in a plane; (ii) inputting a condition .theta.; (iii) segmenting from the plane a rectilinear region S of the pixels to maximize the equation ##EQU1## ;and (iv) outputting data included in the segmented rectilinear region S. The invention also allows regions to be derived which satisfy a desired support maximization rule, confidence maximization rule, optimized entropy rule, and optimized interclass variance rule.Type: GrantFiled: February 18, 1998Date of Patent: November 23, 1999Assignee: International Business Machines CorporationInventors: Takeshi Fukuda, Kunikazu Yoda, Takeshi Tokuyama, Shinichi Morishita -
Patent number: 5983222Abstract: A method is disclosed for computing an association rule in a database having numerical attributes and 0-1 attributes. First, a numerical attribute is divided into a plurality of intervals (or buckets), and each data set is placed into a single bucket according to the value of the numerical attribute. The number of data sets in each bucket and the number of data sets with a 0-1 attribute being 1 are counted. Second, the starting bucket of an interval to be detected is to be detected. Third, the terminating bucket corresponding to the starting bucket is detected. That is, the largest interval with a confidence equal to or larger than a predetermined value. Fourth, one of the detected pairs of starting and terminating buckets which includes the largest number of customers is the answer to this question. Finally, the required data attributes of data included in this interval is subsequently retrieved.Type: GrantFiled: October 25, 1996Date of Patent: November 9, 1999Assignee: International Business Machines CorporationInventors: Yasuhiko Morimoto, Takeshi Fukuda, Shinichi Morishida, Takeshi Tokuyama
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Patent number: 5870748Abstract: A method is disclosed for determining the correlation among data sets having a numerical attribute and a 0-1 attribute. First, a numerical attribute is divided into a plurality of buckets, and each data set is placed into a single bucket according to the value of the numerical attribute. The number of data sets in each bucket and the number of data sets with a 0-1 attribute of 1 are counted. Second, an axis corresponding to the total number of data sets in a first through a particular buckets (X axis) and an axis corresponding to the total number of data sets with a 0-1 attribute of 1 in a first through a particular buckets (Y axis) are virtually established, and points corresponding to the respective values of the first through the particular buckets are virtually plotted. Third, after a plane is constructed in this manner, one of the pairs of points separated at an interval of T.times.N or T or larger which has the largest slope is found.Type: GrantFiled: October 25, 1996Date of Patent: February 9, 1999Assignee: International Business Machines CorporationInventors: Yasuhiko Morimoto, Takeshi Fukuda, Shinichi Morishida, Takeshi Tokuyama
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Patent number: 5812997Abstract: A method is described for finding correlation between a plurality of data having two kinds of numerical attributes and a true-false attribute. The method comprises the steps of: constituting a plane with two numerical attributes, dividing the plane into meshes, and counting the number of data in each mesh (also called a "bucket") and the number of data whose true-false attribute represents true. If each mesh is assumed to be a pixel, such plane can be considered as a plane image in which the number of data corresponds to brilliance, and the number of data whose true-false attribute represents true corresponds to saturation. The method further includes the step of segmenting an admissible image which is convex along an axis of the plane according to a predetermined condition .theta. to find an area with strong correlation. If the segmented area as the admissible image satisfies the above-described condition such as the maximized support rule, the method also presents the area to the user.Type: GrantFiled: October 25, 1996Date of Patent: September 22, 1998Assignee: International Business Machines IncorporatedInventors: Yasuhiko Morimoto, Takeshi Fukuda, Shinichi Morishita, Takeshi Tokuyama
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Patent number: 5729628Abstract: A clear partial image of predetermined size can be segmented at high speed. The method for segmenting a partial image from a whole image comprising a plurality of pixels with gray levels comprises the steps of: inputting a number k of pixels of the partial image to be segmented; detecting a partial image maximizing: ##EQU1## where n is the number of pixels of the whole image, g(i, j) is the gray level of a pixel (i, j), .alpha. is a parameter, and .vertline.S.vertline. is the number of pixels of the partial image S; comparing the number .vertline.S.vertline. of pixels of the partial image S maximizing U.sub..alpha. (S) with the inputted number k; increasing a value of .alpha. if .vertline.S.vertline.>k and decreasing the value of .alpha. if .vertline.S.vertline.<k; again executing the steps subsequent to the specifying step using the updated .alpha.; and outputting said partial image S which maximizes U.sub..alpha. (S) if .vertline.S.vertline.=k.Type: GrantFiled: April 30, 1996Date of Patent: March 17, 1998Assignee: International Business Machines CorporationInventor: Takeshi Tokuyama