Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

Abstract: In order to solve the problem that since a loop filter constant suitable for asynchronous state cannot be selected in the conventional phase frequency synchronism circuit, it takes a long time to synchronize the input data and the clock signal from the asynchronous state, the present invention is to propose a phase frequency synchronism circuit including a phase comparator for generating a voltage according to the phase difference of the clock signal to the input signal, a frequency comparator for deciding if the frequency of the clock signal is higher or lower than the transmission rate of the input signal and generating a binary signal, a synchronous identifying unit for deciding if the input signal and the clock signal are synchronized in their phases and frequencies, a first switch that receives the output from the phase comparator and is closed and opened when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a second switch that receives the output f

Abstract: A mask layer and a to-be-processed layer are irradiated with light to measure interference light formed of reflected lights from the mask layer and reflected lights from the to-be-processed layer. Thereafter, an interference component brought by the mask layer is removed from the waveform of the measured interference light, thereby calculating the waveform of the interference light brought by the to-be-processed layer. The thickness of the remaining to-be-processed layer is determined on the basis of the calculated waveform of the interference light and the thickness of the remaining to-be-processed layer is compared with a desired thickness thereof. In this way, an end point of processing on the to-be-processed layer is detected.

Abstract: A mask layer and a to-be-processed layer are irradiated with light to measure interference light formed of reflected lights from the mask layer and reflected lights from the to-be-processed layer. Thereafter, an interference component brought by the mask layer is removed from the waveform of the measured interference light, thereby calculating the waveform of the interference light brought by the to-be-processed layer. The thickness of the remaining to-be-processed layer is determined on the basis of the calculated waveform of the interference light and the thickness of the remaining to-be-processed layer is compared with a desired thickness thereof. In this way, an end point of processing on the to-be-processed layer is detected.

Abstract: After a hole is formed in a low dielectric constant film on a substrate, a protective film is formed on the wall surface of the hole or an electron acceptor is caused to be adsorbed by or implanted in the low dielectric constant film exposed at the wall surface of the hole. Otherwise, resist residue is left on the wall surface of the hole. Then, a resist pattern having an opening corresponding to a wire formation region including a region formed with the hole is formed by using a chemically amplified resist.

Abstract: A telephone terminal includes: a main unit; an optional unit that performs an arbitrary additional communication function and detachably attached to the main unit; a distribution unit that distributes a drive power supplied through a communication network into a first channel and a second channel when a power of the telephone terminal is turned on; a first power supplying unit that supplies the first channel of the drive power to the main unit at a first timing; and a second power supplying unit that supplies the second channel of the drive power to the optional unit at a second timing shifted from the first timing.

Abstract: A sample & hold type phase detector is used in a CDR IC and, in jitter transfer bandwidth adjustment, VCO output waveforms 90° out of phase with each other can be inputted to the phase detector, whereby a jitter transfer bandwidth can be calculated by only the measurement of frequency and of a DC voltage and it is possible to make a jitter transfer bandwidth adjustment in DC test for IC.

Abstract: A scramble code allocation method used by mobile communications systems, and a base station and a mobile station that use the method are disclosed. The scramble code allocation method autonomously and optimally sets up a scramble code unique to a target base station. The method includes a step of generating a collection packet for collecting unique information of surrounding base stations, the unique information being used for setting up respective identifiers of the surrounding base stations; a step of broadcasting the collection packet to the surrounding base stations through a network; a step of receiving response packets from the surrounding base stations in response to the collection packet; a step of extracting the unique information of the surrounding base stations inserted in the response packets that are received; a step of storing the extracted unique information; and a step of setting up an identifier of the target base station based on the stored unique information.

Abstract: A mask layer and a to-be-processed layer are irradiated with light to measure interference light formed of reflected lights from the mask layer and reflected lights from the to-be-processed layer. Thereafter, an interference component brought by the mask layer is removed from the waveform of the measured interference light, thereby calculating the waveform of the interference light brought by the to-be-processed layer. The thickness of the remaining to-be-processed layer is determined on the basis of the calculated waveform of the interference light and the thickness of the remaining to-be-processed layer is compared with a desired thickness thereof. In this way, an end point of processing on the to-be-processed layer is detected.

Abstract: A method for evaluating an insulating film includes: a first step of forming an insulating film on a semiconductor substrate including a p-n junction therein; a second step of selectively forming an electrode pattern on the insulating film; a third step of forming a measurement electrode on the insulating film so as to be electrically insulated from the electrode pattern; and a fourth step of applying a measurement voltage between the measurement electrode and the semiconductor substrate via the insulating film and measuring a leakage current leaking through the p-n junction so as to evaluate a damage to the insulating film or the semiconductor substrate.

Abstract: In mobile communication system 100 according to the present invention, mobile station 1 is camped on cell C10 established by base station B10. In the cell C10, there exist indoor cells C11-C13 and outdoor cells C21, C22 as neighboring cells. Mobile station 1 measures received levels of cells C10-C13, C21, C22 and determines cell types of the respective cells, i.e., whether each cell is an indoor cell or not, based on broadcast information M1. Mobile station 1 selects a cell as a reselection target on the basis of the received levels and cell types.

Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

Abstract: An electromagnetic relay including a base, an electromagnet incorporated to the base, an armature movably arranged relative to the electromagnet, and a contact section incorporated to the base to be actuated by the armature. The electromagnet includes a bobbin, a coil having a center axis and carried on the bobbin, and a pair of coil terminals mounted to the bobbin. Each of the coil terminals is provided with a first end region and a second end region, extending in respective directions transverse to each other. The coil terminals are disposed in such a manner that respective first end regions extend in a direction transverse to the center axis of the coil to project outward from the bobbin and are arranged side-by-side in a row extending substantially parallel to the center axis, and that respective second end regions extend in a direction parallel to the center axis of the coil to project outward from the bobbin and are arranged side-by-side in a row extending substantially transverse to the center axis.

Abstract: A sample & hold type phase detector is used in a CDR IC and, in jitter transfer bandwidth adjustment, VCO output waveforms 90° out of phase with each other can be inputted to the phase detector, whereby a jitter transfer bandwidth can be calculated by only the measurement of frequency and of a DC voltage and it is possible to make a jitter transfer bandwidth adjustment in DC test for IC.

Abstract: An arithmetic processing section is designed to repeatedly execute product-sum arithmetic processing a number of times equal to the number of samples corresponding to each of the frequencies, in which a value obtained by subtracting a product-sum arithmetic value two sampling periods before from an input signal and a value obtained by multiplying a product-sum arithmetic value one sampling period before by a coefficient corresponding to a reference frequency contained in a DTMF signal are added. A comparator extracts an output value equal to or larger than a predetermined threshold value from the product-sum arithmetic values obtained by the arithmetic processing section. A matrix section determines the type of DTMF signal on the basis of at least two output values extracted by the comparator.

Abstract: In order to solve the problem that since a loop filter constant suitable for asynchronous state cannot be selected in the conventional phase frequency synchronism circuit, it takes a long time to synchronize the input data and the clock signal from the asynchronous state, the present invention is to propose a phase frequency synchronism circuit including a phase comparator for generating a voltage according to the phase difference of the clock signal to the input signal, a frequency comparator for deciding if the frequency of the clock signal is higher or lower than the transmission rate of the input signal and generating a binary signal, a synchronous identifying unit for deciding if the input signal and the clock signal are synchronized in their phases and frequencies, a first switch that receives the output from the phase comparator and is closed and opened when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a second switch that receives the output f

Abstract: After a hole is formed in a low dielectric constant film on a substrate, a protective film is formed on the wall surface of the hole or an electron acceptor is caused to be adsorbed by or implanted in the low dielectric constant film exposed at the wall surface of the hole. Otherwise, resist residue is left on the wall surface of the hole. Then, a resist pattern having an opening corresponding to a wire formation region including a region formed with the hole is formed by using a chemically amplified resist.

Abstract: In order to solve the problem that since a loop filter constant suitable for asynchronous state cannot be selected in the conventional phase frequency synchronism circuit, it takes a long time to synchronize the input data and the clock signal from the asynchronous state, the present invention is to propose a phase frequency synchronism circuit including a phase comparator for generating a voltage according to the phase difference of the clock signal to the input signal, a frequency comparator for deciding if the frequency of the clock signal is higher or lower than the transmission rate of the input signal and generating a binary signal, a synchronous identifying unit for deciding if the input signal and the clock signal are synchronized in their phases and frequencies, a first switch that receives the output from the phase comparator and is closed and opened when the synchronous identifying unit decides that they are synchronized and not synchronized, respectively, a second switch that receives the output f

Abstract: An optical receiver circuit comprising: a pre-amplifier for amplifying a signal supplied from a photodetector to output positive and negative signals; first and second peak hold circuits for detecting maximum levels of these positive and negative signals respectively; an offset canceler circuit for compensating the positive signal at the maximum level of the negative signal, for compensating the negative signal at the maximum level of the positive signal, and for then performing differential amplification; and a level shift circuit for replacing an output signal level of the first peak hold circuit with a signal level higher than an actual value for a period of time that light input to the photodetector is in a no-input signal state.