Abstract: A lead wiring line is provided in a frame region to extend therein while intersecting with a frame-shaped dam wall, is formed of a same material and in a same layer as each of a plurality of display wiring lines in which a first metal layer, a second metal layer, and a third metal layer are layered in sequence, is electrically connected to the plurality of display wiring lines on a display region side, and is electrically connected to a terminal on a terminal portion side. The third metal layer is provided to cover a side surface of the first metal layer, and a side surface and an upper face of the second metal layer.

Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.

Abstract: A display device includes a short ring TFT, wherein the short ring TFT includes a semiconductor layer, a first gate electrode, a second gate electrode, a first gate insulating film provided between the semiconductor layer and the first gate electrode, and a second gate insulating film provided between the semiconductor layer and the second gate electrode, one of a pair of adjacent lead-out wiring lines is electrically connected to a source region of the semiconductor layer, the other of the pair of adjacent lead-out wiring lines is electrically connected to a drain region of the semiconductor layer, one of the first gate electrode and the second gate electrode is electrically connected to the source region or the drain region, and the other of the first gate electrode and the second gate electrode is electrically connected to a threshold value control wiring line.

Abstract: A flexible display device includes a first display region, a second display region, a curved portion, a first high power supply voltage trunk wiring line, and a second high power supply voltage trunk wiring line. A plurality of first high power supply voltage lines branch from the first high power supply voltage trunk wiring line and extend to the first display region, a plurality of second high power supply voltage lines branch from the second high power supply voltage trunk wiring line and extend to the second display region, and the first high power supply voltage trunk wiring line and the second high power supply voltage trunk wiring line are electrically connected to each other via a first curved portion conductive layer formed in the curved portion.

Abstract: An opening, which is provided on the inner side of a first pixel electrode, which is a first electrode formed in a display region, is larger than an opening, which is provided on the inner side of a second pixel electrode, which is the first electrode formed in a dummy display region. Further, a light-emitting layer (a first light-emitting layer) formed in the display region has the same shape and the same size as a light-emitting layer (a second light-emitting layer) formed in the dummy display region.

Abstract: A slit has ends each close to one of a display area and a terminal. The ends are each formed of a stepwise side face, including etch stop films.

Abstract: The present application discloses a current-driven display device capable of providing satisfactory display without flickering even when pause drive is performed. In a pixel circuit 15, a first initialization transistor T4 initializes a gate voltage Vg, and thereafter a voltage on a data signal line Di is written to a holding capacitor Cst via a write control transistor T2 and a drive transistor T1. Thereafter, emission control transistors T5 and T6 are turned on, so that a drive current I1 from the drive transistor T1 causes an organic EL element OL to emit light. During this emission period, even if the gate voltage Vg is decreased due to a leakage current through the first initialization transistor T4 in an OFF state, the decrease is compensated for by increasing a threshold control voltage being provided to a threshold control terminal TG of the drive transistor T1.

Abstract: A display device includes a thin film transistor layer including a first interlayer insulation film, a first wiring layer, a second interlayer insulation film, a second wiring layer, a third interlayer insulation film, a third wiring layer, a first planarization film, a fourth wiring layer, and a second planarization film; and a first damming wall in a frame area separated from the first and second planarization film in a display area by a first slit. There is provided a fourth interlayer insulation film between the third and fourth wiring layer. The fourth interlayer insulation film covers an edge of either one or both of a first frame line and a second frame line as the third wiring layer in a region where the first frame line is located opposite the second frame line in a plan view, the edge facing the display area and being exposed in the first slit.

Abstract: A display device includes a first display region, a second display region, a curved portion provided between the first display region and the second display region, a plurality of first control lines provided in the first display region and extending in a first direction in which the first display region and the second display region are arranged side by side, and a plurality of second control lines provided in the second display region and extending in the first direction. The first control lines and the second control lines are electrically connected via curved portion wiring lines formed in the curved portion.

Abstract: In a TFT layer forming step, first, a semiconductor layer on a resin substrate is formed by performing a semiconductor layer forming step, and subsequently a gate insulating film is formed to cover the semiconductor layer by performing a gate insulating film forming step, and then a first metal layer is formed by performing a first metal film deposition step, a first photo step, and a first etching step, and a second metal layer is formed by performing a second metal film deposition step, a second photo step, and a second etching step, thereby forming a gate layer in which the first metal layer and the second metal layer are layered.

Abstract: A plurality of switching elements are each provided individually between a second high power supply voltage trunk wiring line and each of a plurality of high power supply voltage wiring lines and input a high power supply voltage to a corresponding high power supply voltage wiring line.

Abstract: The display device includes a non-display area. The non-display area includes: a slit formed in an edge cover; a first conductive layer formed in the same layer as an anode, and being in contact with a cathode; and a second conductive layer formed in the same layer as a capacitance electrode and provided to overlap the slit.

Abstract: A TFT layer of a display device includes: an initialization power source wiring line; a second interlayer insulating film provided covering the initialization power source wiring line; a source wiring line provided on the second interlayer insulating film; a low-level power source wiring line provided below the initialization power source wiring line; and a frame capacitor. The frame capacitor includes: a first frame capacitance electrode formed by the same material in the same layer as the initialization power source wiring line; and a second frame capacitance electrode formed by the same material in the same layer as the source wiring line and facing the first frame capacitance electrode with the second interlayer insulating film interposed therebetween. The first frame capacitance electrode is electrically connected to the high-level power source wiring line, and the second frame capacitance electrode is electrically connected to the low-level power source wiring line.

Abstract: A display wiring line provided on a resin substrate layer, a flattening film covering the display wiring line, and an organic EL element provided on the flattening film are provided. The display wiring line includes first to third conductive layers layered sequentially from the resin substrate layer side. In the display wiring line, the second conductive layer is formed with a width smaller than a width of each of the first conductive layer and the third conductive layer, and a portion of a perimeter edge surface corresponding to the second conductive layer includes a recessed portion, and a resin cover covering a perimeter edge surface of the second conductive layer is provided in the recessed portion in a portion of the display wiring line exposed from the flattening film.

Abstract: A first pixel circuit and a third pixel circuit are connected to a first scan signal line, and a second pixel circuit and a fourth pixel circuit are connected to a second scan signal line. Of two first pixel circuits connected to a common, first scan signal line, a capacitive element in the first pixel circuit in a group that is located farther in a row direction from a center of a display area has a larger capacitance value than does a capacitive element in the first pixel circuit in a group that is located closer.

Abstract: A display device includes a base substrate, a thin film transistor layer including an upper layer insulating film and an organic resin layer, a plurality of light-emitting elements provided on the thin film transistor layer and each including a common function layer, a non-display region provided in the display region, an opening provided in the non-display region and passing through the base substrate, and a first frame-shaped protruding portion provided on the upper layer insulating film in a circumferential shape along the opening. The first frame-shaped protruding portion includes a portion where an area of a transverse section parallel to an upper face of the base substrate decreases from an upper face to a bottom face, the common function layer is also provided in the non-display region, and a slit surrounding the first frame-shaped protruding portion is formed in the common function layer provided in the non-display region.

Abstract: A pixel circuit including a drive transistor and a capacitor electrically connected to a control terminal of the drive transistor, a light-emitting element, a first power supply voltage line intersecting a data signal line, and a second power supply voltage line electrically connected to the control terminal via the capacitor are provided, and in a writing period in which a scanning signal line becomes active, the first power supply voltage line and a second conduction terminal of the drive transistor are not conductive with each other, and in a light emission period of the light-emitting element, the first power supply voltage line and the second conduction terminal of the drive transistor are conductive with each other.

Abstract: A separation wall is provided in a frame-like shape along a peripheral edge of a through-hole in a non-display region which is defined to be in an island shape inside a display region and in which the through-hole is formed, the separation wall includes an inner metal layer provided in a frame-like shape on a first inorganic insulating film on a side of the through-hole, and a resin layer provided in a frame-like shape on the first inorganic insulating film and the inner metal layer, and the resin layer includes an inner protrusion portion provided in an eaves shape and protruding from the inner metal layer.

Abstract: A first opening of an edge cover that exposes a first electrode formed in a surface display region is larger than a second opening of an edge cover that exposes a first electrode formed in a side display region, and a light-emitting layer that overlaps the first opening has equal shape and equal size to a light-emitting layer that overlaps the second opening.

Abstract: According to an aspect of the disclosure, a lead wiring line provided in a frame region to extend therein while intersecting with a frame-shaped dam wall, formed of a same material and in a same layer as each of display wiring lines in which a first metal layer, a second metal layer, and a third metal layer are layered in sequence, electrically connected to the display wiring line on a display region side, and electrically connected to a terminal on a terminal portion side, the third metal layer is provided to cover a side surface of the first metal layer, and a side surface and an upper face of the second metal layer.