Patents by Inventor Takeshi Yaneda
Takeshi Yaneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220216288Abstract: A TFT layer of a display device includes: an initialization power source wiring line; a second interlayer insulating film provided covering the initialization power source wiring line; a source wiring line provided on the second interlayer insulating film; a low-level power source wiring line provided below the initialization power source wiring line; and a frame capacitor. The frame capacitor includes: a first frame capacitance electrode formed by the same material in the same layer as the initialization power source wiring line; and a second frame capacitance electrode formed by the same material in the same layer as the source wiring line and facing the first frame capacitance electrode with the second interlayer insulating film interposed therebetween. The first frame capacitance electrode is electrically connected to the high-level power source wiring line, and the second frame capacitance electrode is electrically connected to the low-level power source wiring line.Type: ApplicationFiled: March 28, 2019Publication date: July 7, 2022Inventors: TOHRU OKABE, TAKESHI YANEDA
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Patent number: 11380872Abstract: A display wiring line provided on a resin substrate layer, a flattening film covering the display wiring line, and an organic EL element provided on the flattening film are provided. The display wiring line includes first to third conductive layers layered sequentially from the resin substrate layer side. In the display wiring line, the second conductive layer is formed with a width smaller than a width of each of the first conductive layer and the third conductive layer, and a portion of a perimeter edge surface corresponding to the second conductive layer includes a recessed portion, and a resin cover covering a perimeter edge surface of the second conductive layer is provided in the recessed portion in a portion of the display wiring line exposed from the flattening film.Type: GrantFiled: March 29, 2018Date of Patent: July 5, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Senoo, Takeshi Hirase, Hisao Ochi, Takashi Ochi, Tohru Sonoda, Akihiro Matsui, Jumpei Takahashi, Yoshinobu Miyamoto, Takeshi Yaneda
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Publication number: 20220190097Abstract: A first pixel circuit and a third pixel circuit are connected to a first scan signal line, and a second pixel circuit and a fourth pixel circuit are connected to a second scan signal line. Of two first pixel circuits connected to a common, first scan signal line, a capacitive element in the first pixel circuit in a group that is located farther in a row direction from a center of a display area has a larger capacitance value than does a capacitive element in the first pixel circuit in a group that is located closer.Type: ApplicationFiled: April 26, 2019Publication date: June 16, 2022Inventors: TAMOTSU SAKAI, FUMIYUKI KOBAYASHI, TAKESHI YANEDA
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Publication number: 20220190290Abstract: A display device includes a base substrate, a thin film transistor layer including an upper layer insulating film and an organic resin layer, a plurality of light-emitting elements provided on the thin film transistor layer and each including a common function layer, a non-display region provided in the display region, an opening provided in the non-display region and passing through the base substrate, and a first frame-shaped protruding portion provided on the upper layer insulating film in a circumferential shape along the opening. The first frame-shaped protruding portion includes a portion where an area of a transverse section parallel to an upper face of the base substrate decreases from an upper face to a bottom face, the common function layer is also provided in the non-display region, and a slit surrounding the first frame-shaped protruding portion is formed in the common function layer provided in the non-display region.Type: ApplicationFiled: March 29, 2019Publication date: June 16, 2022Inventors: TAKASHI OCHI, JUMPEI TAKAHASHI, TAKESHI HIRASE, TOHRU SONODA, TSUYOSHI SENZAKI, TAKESHI YANEDA
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Patent number: 11335237Abstract: A pixel circuit including a drive transistor and a capacitor electrically connected to a control terminal of the drive transistor, a light-emitting element, a first power supply voltage line intersecting a data signal line, and a second power supply voltage line electrically connected to the control terminal via the capacitor are provided, and in a writing period in which a scanning signal line becomes active, the first power supply voltage line and a second conduction terminal of the drive transistor are not conductive with each other, and in a light emission period of the light-emitting element, the first power supply voltage line and the second conduction terminal of the drive transistor are conductive with each other.Type: GrantFiled: September 28, 2018Date of Patent: May 17, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Takeshi Yaneda
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Publication number: 20220149121Abstract: A separation wall is provided in a frame-like shape along a peripheral edge of a through-hole in a non-display region which is defined to be in an island shape inside a display region and in which the through-hole is formed, the separation wall includes an inner metal layer provided in a frame-like shape on a first inorganic insulating film on a side of the through-hole, and a resin layer provided in a frame-like shape on the first inorganic insulating film and the inner metal layer, and the resin layer includes an inner protrusion portion provided in an eaves shape and protruding from the inner metal layer.Type: ApplicationFiled: March 1, 2019Publication date: May 12, 2022Applicant: SHARP KABUSHIKI KAISHAInventors: TOHRU OKABE, RYOSUKE GUNJI, SHINSUKE SAIDA, SHINJI ICHIKAWA, HIROHARU JINMURA, YOSHIHIRO NAKADA, AKIRA INOUE, TAKESHI YANEDA
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Publication number: 20220005896Abstract: A first opening of an edge cover that exposes a first electrode formed in a surface display region is larger than a second opening of an edge cover that exposes a first electrode formed in a side display region, and a light-emitting layer that overlaps the first opening has equal shape and equal size to a light-emitting layer that overlaps the second opening.Type: ApplicationFiled: September 26, 2018Publication date: January 6, 2022Inventors: KAORU ABE, TAKESHI YANEDA
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Publication number: 20210351263Abstract: According to an aspect of the disclosure, a lead wiring line provided in a frame region to extend therein while intersecting with a frame-shaped dam wall, formed of a same material and in a same layer as each of display wiring lines in which a first metal layer, a second metal layer, and a third metal layer are layered in sequence, electrically connected to the display wiring line on a display region side, and electrically connected to a terminal on a terminal portion side, the third metal layer is provided to cover a side surface of the first metal layer, and a side surface and an upper face of the second metal layer.Type: ApplicationFiled: September 25, 2018Publication date: November 11, 2021Inventors: TOHRU OKABE, TAKESHI YANEDA
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Publication number: 20210343238Abstract: The present application discloses a current-driven display device capable of providing satisfactory display without flickering even when pause drive is performed. In a pixel circuit 15, a first initialization transistor T4 initializes a gate voltage Vg, and thereafter a voltage on a data signal line Di is written to a holding capacitor Cst via a write control transistor T2 and a drive transistor T1. Thereafter, emission control transistors T5 and T6 are turned on, so that a drive current I1 from the drive transistor T1 causes an organic EL element OL to emit light. During this emission period, even if the gate voltage Vg is decreased due to a leakage current through the first initialization transistor T4 in an OFF state, the decrease is compensated for by increasing a threshold control voltage being provided to a threshold control terminal TG of the drive transistor T1.Type: ApplicationFiled: September 28, 2018Publication date: November 4, 2021Inventors: TOHRU OKABE, TAKESHI YANEDA
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Publication number: 20210343226Abstract: A pixel circuit including a drive transistor and a capacitor electrically connected to a control terminal of the drive transistor, a light-emitting element, a first power supply voltage line intersecting a data signal line, and a second power supply voltage line electrically connected to the control terminal via the capacitor are provided, and in a writing period in which a scanning signal line becomes active, the first power supply voltage line and a second conduction terminal of the drive transistor are not conductive with each other, and in a light emission period of the light-emitting element, the first power supply voltage line and the second conduction terminal of the drive transistor are conductive with each other.Type: ApplicationFiled: September 28, 2018Publication date: November 4, 2021Inventors: TOHRU OKABE, TAKESHI YANEDA
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Publication number: 20210343823Abstract: In a display device, a through-hole and a surrounding region surrounding the through-hole are provided inside an edge of a display region, in which there are provided a first bypass wiring line formed in a first metal layer and bypassing the through-hole in the surrounding region, a first divided wiring line formed in the first metal layer and divided onto one side and the other side of the through-hole, a second bypass wiring line formed in a second metal layer and bypassing the through-hole in the surrounding region, and a second divided wiring line formed in the second metal layer and divided onto one side and the other side of the through-hole.Type: ApplicationFiled: September 28, 2018Publication date: November 4, 2021Inventors: TETSUNORI TANAKA, TAKESHI YANEDA
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Publication number: 20210327996Abstract: A display device includes a short ring TFT, wherein the short ring TFT includes a semiconductor layer, a first gate electrode, a second gate electrode, a first gate insulating film provided between the semiconductor layer and the first gate electrode, and a second gate insulating film provided between the semiconductor layer and the second gate electrode, one of a pair of adjacent lead-out wiring lines is electrically connected to a source region of the semiconductor layer, the other of the pair of adjacent lead-out wiring lines is electrically connected to a drain region of the semiconductor layer, one of the first gate electrode and the second gate electrode is electrically connected to the source region or the drain region, and the other of the first gate electrode and the second gate electrode is electrically connected to a threshold value control wiring line.Type: ApplicationFiled: August 31, 2018Publication date: October 21, 2021Inventors: TOHRU OKABE, TAKESHI YANEDA
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Patent number: 11107845Abstract: A Thin Film Transistor (TFT) substrate includes a first semiconductor film, a first electrically conductive member provided in a layer higher than the first semiconductor film, an interlayer insulating film provided in a layer higher than the first electrically conductive member and including a first through hole, a second semiconductor film provided in a layer higher than the interlayer insulating film, a second electrically conductive member provided in a layer higher than the second semiconductor film, an organic insulating film provided in a layer higher than the second electrically conductive member and including a second through hole, and a third electrically conductive member provided in a layer higher than the organic insulating film. A contact hole extends through the first and the second through hole to the first electrically conductive member.Type: GrantFiled: March 22, 2018Date of Patent: August 31, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
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Publication number: 20210257579Abstract: A display area is provided with a plurality of first conductive layers formed of the same material and in the same layer as first electrodes. The first conductive layers are each positioned under a corresponding one of plurality of first photo spacers. A frame area is provided with a second conductive layer formed of the same material and in the same layer as the first electrodes. The second conductive layer includes a plurality of openings each formed under a corresponding one of a plurality of second photo spacers.Type: ApplicationFiled: August 23, 2018Publication date: August 19, 2021Inventors: TOHRU OKABE, TAKESHI YANEDA
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Patent number: 11024656Abstract: An active matrix substrate in which step-caused disconnection of a metal film in a contact hole does not easily occur includes a first to third insulating films and first to third metal films on a glass substrate and a contact hole electrically connecting the first and second metal film, the contact hole including first to third hole present respectively in the first to third insulating films, the first and third metal films being in contact with each other inside the first hole, the second insulating film and an oxide semiconductor film overlapping with each other in a region below the third hole, the second and third metal films being in contact with each other in a region above the first insulating film and either inside or below the third hole.Type: GrantFiled: June 21, 2017Date of Patent: June 1, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
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Publication number: 20210135159Abstract: A display wiring line provided on a resin substrate layer, a flattening film covering the display wiring line, and an organic EL element provided on the flattening film are provided. The display wiring line includes first to third conductive layers layered sequentially from the resin substrate layer side. In the display wiring line, the second conductive layer is formed with a width smaller than a width of each of the first conductive layer and the third conductive layer, and a portion of a perimeter edge surface corresponding to the second conductive layer includes a recessed portion, and a resin cover covering a perimeter edge surface of the second conductive layer is provided in the recessed portion in a portion of the display wiring line exposed from the flattening film.Type: ApplicationFiled: March 29, 2018Publication date: May 6, 2021Applicant: Sharp Kabushiki KaishaInventors: Tohru SENOO, Takeshi HIRASE, Hisao OCHI, Takashi OCHI, Tohru SONODA, Akihiro MATSUI, Jumpei TAKAHASHI, Yoshinobu MIYAMOTO, Takeshi YANEDA
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Patent number: 10991729Abstract: An active matrix substrate having low susceptibility to contact failure between two conductor films is provided. An oxide semiconductor film converted into a conductor is provided in a layer between a substrate and a first metal film. Within a contact hole, the oxide semiconductor film converted into a conductor is in contact with a second metal film. Outside of the contact hole, the oxide semiconductor film converted into a conductor is in contact with the first metal film.Type: GrantFiled: June 16, 2017Date of Patent: April 27, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
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Publication number: 20210118971Abstract: A plurality of switching elements are each provided individually between a second high power supply voltage trunk wiring line and each of a plurality of high power supply voltage wiring lines and input a high power supply voltage to a corresponding high power supply voltage wiring line.Type: ApplicationFiled: March 22, 2018Publication date: April 22, 2021Applicant: Sharp Kabushiki KaishaInventors: Kuniharu WAKATA, Takeshi YANEDA
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Publication number: 20210066440Abstract: A slit has ends each close to one of a display area and a terminal. The ends are each formed of a stepwise side face, including etch stop films.Type: ApplicationFiled: January 31, 2018Publication date: March 4, 2021Inventors: TOHRU OKABE, RYOSUKE GUNJI, HIROKI TANIYAMA, SHINJI ICHIKAWA, TAKESHI YANEDA, HIROHARU JINMURA, YOSHIHIRO NAKADA, AKIRA INOUE
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Publication number: 20210057510Abstract: A flexible display device includes a first display region, a second display region, a curved portion, a first high power supply voltage trunk wiring line, and a second high power supply voltage trunk wiring line. A plurality of first high power supply voltage lines branch from the first high power supply voltage trunk wiring line and extend to the first display region, a plurality of second high power supply voltage lines branch from the second high power supply voltage trunk wiring line and extend to the second display region, and the first high power supply voltage trunk wiring line and the second high power supply voltage trunk wiring line are electrically connected to each other via a first curved portion conductive layer formed in the curved portion.Type: ApplicationFiled: March 29, 2018Publication date: February 25, 2021Inventors: NORIKO WATANABE, TAKESHI YANEDA