Patents by Inventor Takeshi Yaneda

Takeshi Yaneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210343226
    Abstract: A pixel circuit including a drive transistor and a capacitor electrically connected to a control terminal of the drive transistor, a light-emitting element, a first power supply voltage line intersecting a data signal line, and a second power supply voltage line electrically connected to the control terminal via the capacitor are provided, and in a writing period in which a scanning signal line becomes active, the first power supply voltage line and a second conduction terminal of the drive transistor are not conductive with each other, and in a light emission period of the light-emitting element, the first power supply voltage line and the second conduction terminal of the drive transistor are conductive with each other.
    Type: Application
    Filed: September 28, 2018
    Publication date: November 4, 2021
    Inventors: TOHRU OKABE, TAKESHI YANEDA
  • Publication number: 20210343238
    Abstract: The present application discloses a current-driven display device capable of providing satisfactory display without flickering even when pause drive is performed. In a pixel circuit 15, a first initialization transistor T4 initializes a gate voltage Vg, and thereafter a voltage on a data signal line Di is written to a holding capacitor Cst via a write control transistor T2 and a drive transistor T1. Thereafter, emission control transistors T5 and T6 are turned on, so that a drive current I1 from the drive transistor T1 causes an organic EL element OL to emit light. During this emission period, even if the gate voltage Vg is decreased due to a leakage current through the first initialization transistor T4 in an OFF state, the decrease is compensated for by increasing a threshold control voltage being provided to a threshold control terminal TG of the drive transistor T1.
    Type: Application
    Filed: September 28, 2018
    Publication date: November 4, 2021
    Inventors: TOHRU OKABE, TAKESHI YANEDA
  • Publication number: 20210343823
    Abstract: In a display device, a through-hole and a surrounding region surrounding the through-hole are provided inside an edge of a display region, in which there are provided a first bypass wiring line formed in a first metal layer and bypassing the through-hole in the surrounding region, a first divided wiring line formed in the first metal layer and divided onto one side and the other side of the through-hole, a second bypass wiring line formed in a second metal layer and bypassing the through-hole in the surrounding region, and a second divided wiring line formed in the second metal layer and divided onto one side and the other side of the through-hole.
    Type: Application
    Filed: September 28, 2018
    Publication date: November 4, 2021
    Inventors: TETSUNORI TANAKA, TAKESHI YANEDA
  • Publication number: 20210327996
    Abstract: A display device includes a short ring TFT, wherein the short ring TFT includes a semiconductor layer, a first gate electrode, a second gate electrode, a first gate insulating film provided between the semiconductor layer and the first gate electrode, and a second gate insulating film provided between the semiconductor layer and the second gate electrode, one of a pair of adjacent lead-out wiring lines is electrically connected to a source region of the semiconductor layer, the other of the pair of adjacent lead-out wiring lines is electrically connected to a drain region of the semiconductor layer, one of the first gate electrode and the second gate electrode is electrically connected to the source region or the drain region, and the other of the first gate electrode and the second gate electrode is electrically connected to a threshold value control wiring line.
    Type: Application
    Filed: August 31, 2018
    Publication date: October 21, 2021
    Inventors: TOHRU OKABE, TAKESHI YANEDA
  • Patent number: 11107845
    Abstract: A Thin Film Transistor (TFT) substrate includes a first semiconductor film, a first electrically conductive member provided in a layer higher than the first semiconductor film, an interlayer insulating film provided in a layer higher than the first electrically conductive member and including a first through hole, a second semiconductor film provided in a layer higher than the interlayer insulating film, a second electrically conductive member provided in a layer higher than the second semiconductor film, an organic insulating film provided in a layer higher than the second electrically conductive member and including a second through hole, and a third electrically conductive member provided in a layer higher than the organic insulating film. A contact hole extends through the first and the second through hole to the first electrically conductive member.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 31, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Publication number: 20210257579
    Abstract: A display area is provided with a plurality of first conductive layers formed of the same material and in the same layer as first electrodes. The first conductive layers are each positioned under a corresponding one of plurality of first photo spacers. A frame area is provided with a second conductive layer formed of the same material and in the same layer as the first electrodes. The second conductive layer includes a plurality of openings each formed under a corresponding one of a plurality of second photo spacers.
    Type: Application
    Filed: August 23, 2018
    Publication date: August 19, 2021
    Inventors: TOHRU OKABE, TAKESHI YANEDA
  • Patent number: 11024656
    Abstract: An active matrix substrate in which step-caused disconnection of a metal film in a contact hole does not easily occur includes a first to third insulating films and first to third metal films on a glass substrate and a contact hole electrically connecting the first and second metal film, the contact hole including first to third hole present respectively in the first to third insulating films, the first and third metal films being in contact with each other inside the first hole, the second insulating film and an oxide semiconductor film overlapping with each other in a region below the third hole, the second and third metal films being in contact with each other in a region above the first insulating film and either inside or below the third hole.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: June 1, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Publication number: 20210135159
    Abstract: A display wiring line provided on a resin substrate layer, a flattening film covering the display wiring line, and an organic EL element provided on the flattening film are provided. The display wiring line includes first to third conductive layers layered sequentially from the resin substrate layer side. In the display wiring line, the second conductive layer is formed with a width smaller than a width of each of the first conductive layer and the third conductive layer, and a portion of a perimeter edge surface corresponding to the second conductive layer includes a recessed portion, and a resin cover covering a perimeter edge surface of the second conductive layer is provided in the recessed portion in a portion of the display wiring line exposed from the flattening film.
    Type: Application
    Filed: March 29, 2018
    Publication date: May 6, 2021
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Tohru SENOO, Takeshi HIRASE, Hisao OCHI, Takashi OCHI, Tohru SONODA, Akihiro MATSUI, Jumpei TAKAHASHI, Yoshinobu MIYAMOTO, Takeshi YANEDA
  • Patent number: 10991729
    Abstract: An active matrix substrate having low susceptibility to contact failure between two conductor films is provided. An oxide semiconductor film converted into a conductor is provided in a layer between a substrate and a first metal film. Within a contact hole, the oxide semiconductor film converted into a conductor is in contact with a second metal film. Outside of the contact hole, the oxide semiconductor film converted into a conductor is in contact with the first metal film.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 27, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Publication number: 20210118971
    Abstract: A plurality of switching elements are each provided individually between a second high power supply voltage trunk wiring line and each of a plurality of high power supply voltage wiring lines and input a high power supply voltage to a corresponding high power supply voltage wiring line.
    Type: Application
    Filed: March 22, 2018
    Publication date: April 22, 2021
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kuniharu WAKATA, Takeshi YANEDA
  • Publication number: 20210066440
    Abstract: A slit has ends each close to one of a display area and a terminal. The ends are each formed of a stepwise side face, including etch stop films.
    Type: Application
    Filed: January 31, 2018
    Publication date: March 4, 2021
    Inventors: TOHRU OKABE, RYOSUKE GUNJI, HIROKI TANIYAMA, SHINJI ICHIKAWA, TAKESHI YANEDA, HIROHARU JINMURA, YOSHIHIRO NAKADA, AKIRA INOUE
  • Publication number: 20210057510
    Abstract: A flexible display device includes a first display region, a second display region, a curved portion, a first high power supply voltage trunk wiring line, and a second high power supply voltage trunk wiring line. A plurality of first high power supply voltage lines branch from the first high power supply voltage trunk wiring line and extend to the first display region, a plurality of second high power supply voltage lines branch from the second high power supply voltage trunk wiring line and extend to the second display region, and the first high power supply voltage trunk wiring line and the second high power supply voltage trunk wiring line are electrically connected to each other via a first curved portion conductive layer formed in the curved portion.
    Type: Application
    Filed: March 29, 2018
    Publication date: February 25, 2021
    Inventors: NORIKO WATANABE, TAKESHI YANEDA
  • Publication number: 20210036093
    Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 4, 2021
    Inventors: TOHRU OKABE, SHINSUKE SAIDA, SHINJI ICHIKAWA, HIROKI TANIYAMA, RYOSUKE GUNJI, KOHJI ARIGA, YOSHIHIRO NAKADA, KOJI TANIMURA, YOSHIHIRO KOHARA, AKIRA INOUE, HIROHARU JINMURA, TAKESHI YANEDA
  • Publication number: 20210020732
    Abstract: A display device includes a first display region, a second display region, a curved portion provided between the first display region and the second display region, a plurality of first control lines provided in the first display region and extending in a first direction in which the first display region and the second display region are arranged side by side, and a plurality of second control lines provided in the second display region and extending in the first direction. The first control lines and the second control lines are electrically connected via curved portion wiring lines formed in the curved portion.
    Type: Application
    Filed: March 29, 2018
    Publication date: January 21, 2021
    Inventors: NORIKO WATANABE, TAKESHI YANEDA
  • Publication number: 20210020719
    Abstract: An opening, which is provided on the inner side of a first pixel electrode, which is a first electrode formed in a display region, is larger than an opening, which is provided on the inner side of a second pixel electrode, which is the first electrode formed in a dummy display region. Further, a light-emitting layer (a first light-emitting layer) formed in the display region has the same shape and the same size as a light-emitting layer (a second light-emitting layer) formed in the dummy display region.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 21, 2021
    Inventors: KAORU ABE, TAKESHI YANEDA
  • Publication number: 20210013297
    Abstract: The display device includes a non-display area. The non-display area includes: a slit formed in an edge cover; a first conductive layer formed in the same layer as an anode, and being in contact with a cathode; and a second conductive layer formed in the same layer as a capacitance electrode and provided to overlap the slit.
    Type: Application
    Filed: March 30, 2018
    Publication date: January 14, 2021
    Inventors: TOHRU OKABE, SHINSUKE SAIDA, SHINJI ICHIKAWA, HIROKI TANIYAMA, RYOSUKE GUNJI, TAKESHI YANEDA, YOSHIHIRO NAKADA, HIROHARU JINMURA, AKIRA INOUE
  • Publication number: 20200381462
    Abstract: An embodiment of the present invention provides, in a TFT substrate having a lower layer portion and an upper layer portion each including a respective semiconductor film, a stable connection between an electrically conductive member of the lower layer portion and an electrically conductive member of the upper layer portion.
    Type: Application
    Filed: March 22, 2018
    Publication date: December 3, 2020
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Takeshi YANEDA
  • Patent number: 10847739
    Abstract: Openings, which are provided on the inner sides of anode electrodes formed in a display region, are larger than openings, which are provided on the inner sides of anode electrodes formed in a peripheral display region. A light-emitting layer formed in the display region has equal shape and equal size to a light-emitting layer formed in the peripheral display region.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: November 24, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Abe, Takeshi Yaneda
  • Patent number: 10840269
    Abstract: A semiconductor device provided in a pixel circuit of a display device includes, in order from a lower side: a substrate; an LTPS layer; a first gate insulating layer; a first metal layer; a first flattened layer; a second gate insulating layer; an oxide semiconductor layer; a second metal layer; a passivation layer; and a third metal layer. The gate electrode layer of an LTPS-TFT and the gate electrode of an oxide semiconductor TFT are formed by the first metal layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 17, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Tetsunori Tanaka, Takeshi Yaneda
  • Publication number: 20200328235
    Abstract: An active matrix substrate having low susceptibility to contact failure between two conductor films is provided. An oxide semiconductor film converted into a conductor is provided in a layer between a substrate and a first metal film. Within a contact hole, the oxide semiconductor film converted into a conductor is in contact with a second metal film. Outside of the contact hole, the oxide semiconductor film converted into a conductor is in contact with the first metal film.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 15, 2020
    Inventors: Tohru OKABE, Hirohiko NISHIKI, Takeshi YANEDA