Patents by Inventor Takeshi Yuzawa

Takeshi Yuzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10658325
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and his a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: May 19, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Publication number: 20190019773
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and his a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Application
    Filed: September 17, 2018
    Publication date: January 17, 2019
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takeshi YUZAWA, Masatoshi TAGAKI
  • Patent number: 10103120
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 16, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Publication number: 20180076138
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takeshi YUZAWA, Masatoshi TAGAKI
  • Patent number: 9842821
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: December 12, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Publication number: 20170077058
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Inventors: Takeshi YUZAWA, Masatoshi TAGAKI
  • Patent number: 9515043
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 6, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Publication number: 20160225732
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Application
    Filed: March 29, 2016
    Publication date: August 4, 2016
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takeshi YUZAWA, Masatoshi TAGAKI
  • Patent number: 9331039
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 3, 2016
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Publication number: 20150287690
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire couple part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Takeshi YUZAWA, Masatoshi TAGAKI
  • Patent number: 9093334
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: July 28, 2015
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Publication number: 20150102489
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 16, 2015
    Inventors: Takeshi YUZAWA, Masatoshi TAGAKI
  • Patent number: 8952554
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: February 10, 2015
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Publication number: 20140361433
    Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.
    Type: Application
    Filed: August 25, 2014
    Publication date: December 11, 2014
    Inventors: Takeshi YUZAWA, Masatoshi TAGAKI
  • Patent number: 8878365
    Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: November 4, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Publication number: 20140217583
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively.
    Type: Application
    Filed: April 14, 2014
    Publication date: August 7, 2014
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takeshi YUZAWA, Masatoshi TAGAKI
  • Patent number: 8742601
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: June 3, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Publication number: 20140048933
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively.
    Type: Application
    Filed: October 30, 2013
    Publication date: February 20, 2014
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takeshi YUZAWA, Masatoshi TAGAKI
  • Patent number: 8614513
    Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively. The buffer layer is made of a material other than resin and softer than the inorganic insulating layer.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 24, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki
  • Patent number: 8441125
    Abstract: A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric and covering the active region when viewed from a top side; and a forbidden region provided in the semiconductor layer in a specific range positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad. A connection section at which the first conductive layer and the second conductive layer are connected is not provided in the forbidden region.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: May 14, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Takeshi Yuzawa, Masatoshi Tagaki