Patents by Inventor Takeshi Yuzawa
Takeshi Yuzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120032324Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.Type: ApplicationFiled: October 14, 2011Publication date: February 9, 2012Applicant: SEIKO EPSON CORPORATIONInventors: Takeshi YUZAWA, Masatoshi TAGAKI
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Publication number: 20110169161Abstract: A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric and covering the active region when viewed from a top side; and a forbidden region provided in the semiconductor layer in a specific range positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad. A connection section at which the first conductive layer and the second conductive layer are connected is not provided in the forbidden region.Type: ApplicationFiled: March 28, 2011Publication date: July 14, 2011Applicant: SEIKO EPSON CORPORATIONInventors: TAKESHI Yuzawa, MASATOSHI Tagaki
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Patent number: 7936064Abstract: A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric and covering the active region when viewed from a top side; and a forbidden region provided in the semiconductor layer in a specific range positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad. A connection section at which the first conductive layer and the second conductive layer are connected is not provided in the forbidden region.Type: GrantFiled: May 31, 2006Date of Patent: May 3, 2011Assignee: Seiko Epson CorporationInventors: Takeshi Yuzawa, Masatoshi Tagaki
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Patent number: 7598612Abstract: A semiconductor device including a semiconductor substrate containing a plurality of electrode pads and a passivation film with an opening that exposes a central area of each of the electrode pads, and a bump electrically connected to each of the electrode pads, the bump being disposed to overlap the opening and an end of the opening, wherein at least part of an area contacting the bump on a surface of the passivation film is an uneven surface.Type: GrantFiled: November 1, 2005Date of Patent: October 6, 2009Assignee: Seiko Epson CorporationInventor: Takeshi Yuzawa
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Patent number: 7560814Abstract: A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with the electrode pad; a passivation film formed to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; a bump formed to be larger than the opening in the passivation film and to be partially positioned on the passivation film; and a barrier layer which lies between the electrode pad and the bump. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.Type: GrantFiled: May 3, 2007Date of Patent: July 14, 2009Assignee: Seiko Epson CorporationInventors: Takeshi Yuzawa, Hideki Yuzawa, Michiyoshi Takano
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Publication number: 20090035929Abstract: A method of manufacturing a semiconductor device includes: (a) forming an insulating layer having a contact hole on a semiconductor section in which an element is formed; (b) forming an electrode pad on the insulating layer so that a depression or a protrusion remains at a position at which the electrode pad overlaps the contact section; (c) forming a passivation film to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; (d) forming a barrier layer on the electrode pad; and (e) forming a bump to be larger than the opening in the passivation film and to be partially positioned on the passivation film. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.Type: ApplicationFiled: October 2, 2007Publication date: February 5, 2009Applicant: Seiko Epson CorporationInventors: Takeshi Yuzawa, Hideki Yuzawa, Michiyoshi Takano
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Publication number: 20070257363Abstract: A semiconductor device includes a semiconductor chip, wiring that is included in the semiconductor chip and has a coupling part between parts with different widths, a pad being formed above the wiring and in a position overlapping the coupling part, a bump being formed on the pad, a buffer layer being formed in a position between the coupling part and the pad so as to cover the entire coupling part, and inorganic insulating layers being formed between the wiring and the buffer layer and between the buffer layer and the pad, respectively.Type: ApplicationFiled: April 20, 2007Publication date: November 8, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Takeshi YUZAWA, Masatoshi TAGAKI
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Publication number: 20070228560Abstract: A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with the electrode pad; a passivation film formed to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; a bump formed to be larger than the opening in the passivation film and to be partially positioned on the passivation film; and a barrier layer which lies between the electrode pad and the bump. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.Type: ApplicationFiled: May 3, 2007Publication date: October 4, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Takeshi Yuzawa, Hideki Yuzawa, Michiyoshi Takano
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Patent number: 7230338Abstract: A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with the electrode pad; a passivation film formed to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; a bump formed to be larger than the opening in the passivation film and to be partially positioned on the passivation film; and a barrier layer which lies between the electrode pad and the bump. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.Type: GrantFiled: June 2, 2005Date of Patent: June 12, 2007Assignee: Seiko Epson CorporationInventors: Takeshi Yuzawa, Hideki Yuzawa, Michiyoshi Takano
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Publication number: 20070035022Abstract: A semiconductor device, including: a semiconductor layer; an electrode pad formed above the semiconductor layer; an insulating layer formed over the electrode pad and having an opening which exposes at least part of the electrode pad; and a bump formed at least in the opening. The bump includes: a first bump layer formed in the opening; an underlayer formed above the first bump layer and the insulating layer positioned around the first bump layer; and a second bump layer formed on the underlayer.Type: ApplicationFiled: August 8, 2006Publication date: February 15, 2007Inventor: Takeshi Yuzawa
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Patent number: 7176581Abstract: A surface, which is opposite to a plane polygon of a resin layer, includes a third side opposed to a first side of the plane polygon, and a fourth side oppose to a second side of the plane polygon. A first space between the first side and third side is narrower than a second space between the second side and fourth side. A plurality of electrodes are arranged in a first region located between the second side and the fourth side and are spaced apart from a second region located between the first side and the third side. The third side comprises a first curved line and a pair of second curved lines connected to both ends of the first curved line. The first curved line is convexly bent toward the inside of the resin layer and each of the second curved lines is convexly bent toward the outside of the resin layer.Type: GrantFiled: April 25, 2005Date of Patent: February 13, 2007Assignee: Seiko Epson CorporationInventor: Takeshi Yuzawa
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Publication number: 20070018317Abstract: A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric and covering the active region when viewed from a top side; and a forbidden region provided in the semiconductor layer in a specific range positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad. A connection section at which the first conductive layer and the second conductive layer are connected is not provided in the forbidden region.Type: ApplicationFiled: May 31, 2006Publication date: January 25, 2007Inventors: Takeshi Yuzawa, Masatoshi Tagaki
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Publication number: 20070013065Abstract: A semiconductor device, including: a semiconductor layer; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width which is smaller than the first width; an interlayer dielectric formed above the first conductive layer and the second conductive layer; and an electrode pad formed above the interlayer dielectric. A connection section at which the first conductive layer and the second conductive layer are connected is disposed in a specific region positioned inward from a line extending vertically downward from an edge of the electrode pad; and a reinforcing section is provided at the connection section.Type: ApplicationFiled: June 8, 2006Publication date: January 18, 2007Inventors: Takeshi Yuzawa, Masatoshi Tagaki
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Publication number: 20060125095Abstract: A semiconductor device including a semiconductor substrate containing a plurality of electrode pads and a passivation film with an opening that exposes a central area of each of the electrode pads, and a bump electrically connected to each of the electrode pads, the bump being disposed to overlap the opening and an end of the opening, wherein at least part of an area contacting the bump on a surface of the passivation film is an uneven surface.Type: ApplicationFiled: November 1, 2005Publication date: June 15, 2006Applicant: SEIKO EPSON CORPORATIONInventor: Takeshi Yuzawa
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Patent number: 7037758Abstract: The invention provides a method of manufacturing a semiconductor that improves the productivity and the yield of a product, and grinds a semiconductor substrate so that it has almost uniform thickness. The method can include forming a protrusion on a semiconductor substrate having a first area and a second area surrounding the first area. The protrusion protruding above first area. A support being disposed on a surface on which the protrusion is formed, of the semiconductor substrate so that a through hole of the support overlaps with the first area. The semiconductor substrate can be grinded from a surface opposite to the surface on which the protrusion is formed.Type: GrantFiled: August 19, 2003Date of Patent: May 2, 2006Assignee: Seiko Epson CorporationInventors: Fumiaki Karasawa, Takeshi Yuzawa
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Publication number: 20050272243Abstract: A method of manufacturing a semiconductor device includes: (a) forming an insulating layer having a contact hole on a semiconductor section in which an element is formed; (b) forming an electrode pad on the insulating layer so that a depression or a protrusion remains at a position at which the electrode pad overlaps the contact section; (c) forming a passivation film to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; (d) forming a barrier layer on the electrode pad; and (e) forming a bump to be larger than the opening in the passivation film and to be partially positioned on the passivation film. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.Type: ApplicationFiled: June 2, 2005Publication date: December 8, 2005Applicant: SEIKO EPSON CORPORATIONInventors: Takeshi Yuzawa, Hideki Yuzawa, Michiyoshi Takano
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Publication number: 20050269697Abstract: A semiconductor device including: a semiconductor section in which an element is formed; an insulating layer formed on the semiconductor section; an electrode pad formed on the insulating layer; a contact section formed of a conductive material provided in a contact hole in the insulating layer and electrically connected with the electrode pad; a passivation film formed to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; a bump formed to be larger than the opening in the passivation film and to be partially positioned on the passivation film; and a barrier layer which lies between the electrode pad and the bump. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad.Type: ApplicationFiled: June 2, 2005Publication date: December 8, 2005Applicant: SEIKO EPSON CORPORATIONInventors: Takeshi Yuzawa, Hideki Yuzawa, Michiyoshi Takano
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Publication number: 20050253260Abstract: A surface, which is opposite to a plane polygon of a resin layer, includes a third side opposed to a first side of the plane polygon, and a fourth side oppose to a second side of the plane polygon. A first space between the first side and third side is narrower than a second space between the second side and fourth side. A plurality of electrodes are arranged in a first region located between the second side and the fourth side and are spaced apart from a second region located between the first side and the third side. The third side comprises a first curved line and a pair of second curved lines connected to both ends of the first curved line. The first curved line is convexly bent toward the inside of the resin layer and each of the second curved lines is convexly bent toward the outside of the resin layer.Type: ApplicationFiled: April 25, 2005Publication date: November 17, 2005Inventor: Takeshi Yuzawa
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Publication number: 20040180549Abstract: (PROBLEM) To improve the productivity and the yield of a product, and to grind a semiconductor substrate so that it has almost uniform thickness. (MEANS TO SOLVE THE PROBLEM) A protrusion 40 is formed on a semiconductor substrate 10 having a first area 20 and a second area 30 surrounding the first area 20, the protrusion 40 protruding above first area 20. A support 60 is disposed on a surface on which the protrusion 40 is formed, of the semiconductor substrate 10 so that a through hole 61 of the support 60 overlaps with the first area 20. The semiconductor substrate 10is grinded from a surface opposite to the surface on which the protrusion 40 is formed.Type: ApplicationFiled: August 19, 2003Publication date: September 16, 2004Applicant: Seiko Epson CorporationInventors: Fumiaki Karasawa, Takeshi Yuzawa