Patents by Inventor Taku Nishiyama
Taku Nishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230187304Abstract: A semiconductor device includes a substrate, an insulating layer that is provided on the substrate and has multiple openings, a semiconductor chip that is provided on the substrate and has a first face, on which a semiconductor element is formed, and a second face, which opposes the first face and faces the substrate, multiple protrusions provided on the substrate in positions corresponding to the multiple openings of the insulating layer between the substrate and the second face, a height of the multiple protrusions in a direction vertical to the second face is greater than a height of the insulating layer in a direction vertical to the second face, and a bonding layer that is provided between the substrate and the second face to bond the substrate and the semiconductor chip, and has a thermal conductivity that is more than 1 W/(m·K).Type: ApplicationFiled: July 29, 2022Publication date: June 15, 2023Inventor: Taku NISHIYAMA
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Publication number: 20210055866Abstract: According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.Type: ApplicationFiled: October 21, 2020Publication date: February 25, 2021Applicant: Kioxia CorporationInventors: Akihisa FUJIMOTO, Atsushi KONDO, Noriya SAKAMOTO, Taku NISHIYAMA, Katsuyoshi WATANABE
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Patent number: 10714853Abstract: According to one embodiment, a semiconductor storage device includes a housing, a plurality of terminals, signal terminals, a controller, signal wiring, and a memory. The housing has a first face and a second face opposite to the first face. The plurality of terminals is exposed to the first face, extends in a first direction, and is spaced apart in a second direction intersecting with the first direction. A signal terminal included in the plurality of terminals has a first end in the first direction, and a second end opposite to the first end in the first direction, the second end being closer to a contact position with a socket contact than the first end. The controller is located in the housing. The signal wiring extends from the first end in the housing and electrically connects the first end and the controller. The memory is electrically connected to the controller in the housing.Type: GrantFiled: February 27, 2019Date of Patent: July 14, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Toshitada Saito, Hideki Kawamura, Atsushi Kondo, Katsuyoshi Watanabe, Taku Nishiyama
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Publication number: 20190393633Abstract: According to one embodiment, a semiconductor storage device includes a housing, a plurality of terminals, signal terminals, a controller, signal wiring, and a memory. The housing has a first face and a second face opposite to the first face. The plurality of terminals is exposed to the first face, extends in a first direction, and is spaced apart in a second direction intersecting with the first direction. A signal terminal included in the plurality of terminals has a first end in the first direction, and a second end opposite to the first end in the first direction, the second end being closer to a contact position with a socket contact than the first end. The controller is located in the housing. The signal wiring extends from the first end in the housing and electrically connects the first end and the controller. The memory is electrically connected to the controller in the housing.Type: ApplicationFiled: February 27, 2019Publication date: December 26, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Toshitada Saito, Hideki Kawamura, Atsushi Kondo, Katsuyoshi Watanabe, Taku Nishiyama
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Patent number: 10249934Abstract: A memory card includes a substrate, a nonvolatile memory on the substrate, a memory controller on the substrate and configured to control access to the nonvolatile memory, an interface terminal for external wired connection, on the substrate, an antenna, a plain region surrounded by the antenna including a first region that overlaps with the substrate and a second region that does not overlap with the substrate, and a communication controller disposed on the substrate, electrically connected to the antenna, and configured to wirelessly communicate with an external device through the antenna, using power generated at the antenna by an electromagnetic induction caused by the external device.Type: GrantFiled: September 1, 2016Date of Patent: April 2, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tsubasa Natsumeda, Michio Ido, Keisuke Sato, Shigeto Endo, Taku Nishiyama, Katsuyoshi Watanabe
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Publication number: 20170155184Abstract: A memory card includes a substrate, a nonvolatile memory on the substrate, a memory controller on the substrate and configured to control access to the nonvolatile memory, an interface terminal for external wired connection, on the substrate, an antenna, a plain region surrounded by the antenna including a first region that overlaps with the substrate and a second region that does not overlap with the substrate, and a communication controller disposed on the substrate, electrically connected to the antenna, and configured to wirelessly communicate with an external device through the antenna, using power generated at the antenna by an electromagnetic induction caused by the external device.Type: ApplicationFiled: September 1, 2016Publication date: June 1, 2017Inventors: Tsubasa NATSUMEDA, Michio IDO, Keisuke SATO, Shigeto ENDO, Taku NISHIYAMA, Katsuyoshi WATANABE
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Patent number: 9236329Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.Type: GrantFiled: March 5, 2013Date of Patent: January 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhide Doi, Soichi Homma, Katsuyoshi Watanabe, Taku Nishiyama, Takeshi Ikuta, Naohisa Okumura
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Publication number: 20150357280Abstract: According to one embodiment, a memory card is disclosed. The memory card includes a substrate, a memory provided on the substrate, a controller provided on the substrate, and a first interconnect provided on the substrate. A distance between an edge of the substrate and the first interconnect is greater than or equal to 0.4 mm. The memory card further includes a resin covering the memory, the controller and the interconnect. The resin includes a first region and a second region, the amount of carbide in the first region is larger than the amount of carbide in the second region.Type: ApplicationFiled: September 10, 2014Publication date: December 10, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Akihiro IIDA, Taku NISHIYAMA
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Patent number: 9202768Abstract: According to one embodiment, a semiconductor module has a substrate, two nonvolatile memories disposed on a first surface of the substrate, a controller to control the nonvolatile memories, disposed on the first surface of the substrate and between the two nonvolatile memories, and a plurality of terminals that are electrically connected to the two nonvolatile memories and to the controller, disposed on a second surface of the substrate.Type: GrantFiled: March 7, 2013Date of Patent: December 1, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hideo Aoki, Katsuhiko Oyama, Taku Nishiyama, Chiaki Takubo, Katsuya Sakai
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Patent number: 9165870Abstract: According to the embodiment, a semiconductor storage device includes an organic substrate, a semiconductor memory chip, a lead frame, and a resin mold section. The lead frame includes an adhering portion. The organic substrate is singulated to have a shape in which a portion in which the organic substrate does not overlap with the placing portion is larger than a portion in which the organic substrate overlaps with the placing portion, in plan view. The lead frame further includes a first extending portion in the adhering portion that extends to a surface different from a surface of the resin mold section on a side of an insertion direction.Type: GrantFiled: June 24, 2011Date of Patent: October 20, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hitoshi Ishii, Naohisa Okumura, Taku Nishiyama
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Patent number: 9033248Abstract: According to one embodiment, a semiconductor storage device is provided with a memory chip including a storage circuit, a controller chip that controls a memory chip, and a substrate having a first surface and a second surface opposing one another, on the first surface of which the controller chip is mounted. Further, the semiconductor storage device is provided with an external connection terminal formed on the second surface of the substrate, and resin that encapsulates the memory chip, the controller chip, and the substrate, includes a third surface and a fourth surface opposing one another, and has a predetermined mark directly printed only on the fourth surface that is adjacent to the second surface of the substrate.Type: GrantFiled: July 20, 2012Date of Patent: May 19, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hidetoshi Suzuki, Yuichi Hotta, Yuji Shimoda, Yuuji Ogawa, Taku Nishiyama, Tadanobu Okubo, Junichi Onodera, Takeshi Ikuta, Naohisa Okumura, Katsuyoshi Watanabe, Kazuhide Doi
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Publication number: 20140252588Abstract: According to one embodiment, a semiconductor module has a substrate, two nonvolatile memories disposed on a first surface of the substrate, a controller to control the nonvolatile memories, disposed on the first surface of the substrate and between the two nonvolatile memories, and a plurality of terminals that are electrically connected to the two nonvolatile memories and to the controller, disposed on a second surface of the substrate.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hideo AOKI, Katsuhiko Oyama, Taku Nishiyama, Chiaki Takubo, Katsuya Sakai
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Publication number: 20140168914Abstract: According to one embodiment, a semiconductor device includes a board and a semiconductor chip. The semiconductor chip includes a portion located outside the board in an extension direction of the board and a portion overlapping the board or an end face substantially aligned with an edge of the board in a thickness direction of the board.Type: ApplicationFiled: April 23, 2013Publication date: June 19, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshiro YOKOYAMA, Taku NISHIYAMA, Yuji SHIMODA, Yuuji OGAWA
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Publication number: 20140070381Abstract: A semiconductor memory card includes a lead frame having external connection terminals, a controller chip mounted on the lead frame and a memory chip mounted on the lead frame. The lead frame, the controller chip, and the memory chip are sealed with a sealing resin layer that has a surface at which the external connection terminals are exposed and a recess surrounding the external connection terminals.Type: ApplicationFiled: March 5, 2013Publication date: March 13, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuhide DOI, Soichi HOMMA, Katsuyoshi WATANABE, Taku NISHIYAMA, Takeshi IKUTA, Naohisa OKUMURA
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Patent number: 8581372Abstract: According to one embodiment, a semiconductor storage device includes a plate and an external connection terminal. The plate is molded in a resin mold section. A semiconductor memory chip is placed on the plate. The external connection terminal is exposed to the outer circumferential surface of the semiconductor storage device. The plate includes a plurality of exposed portions exposed to the outer circumferential surface of the resin mold section. The plurality of exposed portions is electrically insulated from each other inside the resin mold section.Type: GrantFiled: March 18, 2011Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Junichi Asada, Taku Nishiyama, Atsuko Seki
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Patent number: 8575738Abstract: In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer.Type: GrantFiled: February 29, 2012Date of Patent: November 5, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhide Doi, Naohisa Okumura, Taku Nishiyama, Katsuyoshi Watanabe, Takeshi Ikuta
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Publication number: 20130186960Abstract: According to one embodiment, a semiconductor storage device is provided with a memory chip including a storage circuit, a controller chip that controls a memory chip, and a substrate having a first surface and a second surface opposing one another, on the first surface of which the controller chip is mounted. Further, the semiconductor storage device is provided with an external connection terminal formed on the second surface of the substrate, and resin that encapsulates the memory chip, the controller chip, and the substrate, includes a third surface and a fourth surface opposing one another, and has a predetermined mark directly printed only on the fourth surface that is adjacent to the second surface of the substrate.Type: ApplicationFiled: July 20, 2012Publication date: July 25, 2013Inventors: Hidetoshi SUZUKI, Yuichi Hotta, Yuji Shimoda, Yuuji Ogawa, Taku Nishiyama, Tadanobu Okubo, Junichi Onodera, Takeshi Ikuta, Naohisa Okumura, Katsuyoshi Watanabe, Kazuhide Doi
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Patent number: 8395268Abstract: A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element gType: GrantFiled: June 29, 2011Date of Patent: March 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Tetsuya Yamamoto, Naohisa Okumura
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Patent number: D900827Type: GrantFiled: July 31, 2018Date of Patent: November 3, 2020Assignee: KIOXIA CORPORATIONInventors: Atsushi Kondo, Taku Nishiyama, Katsuyoshi Watanabe
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Patent number: D902164Type: GrantFiled: June 27, 2019Date of Patent: November 17, 2020Assignee: Toshiba Memory CorporationInventors: Atsushi Kondo, Taku Nishiyama, Katsuyoshi Watanabe