Patents by Inventor Taku Nishiyama
Taku Nishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8376238Abstract: According to one embodiment, a semiconductor device includes a memory chip and a controller chip. A circuit board includes a first surface on which an array of external connection terminals are provided and an second surface on which the memory and controller chips are provided. An array of connection pads is provided on the second surface and outside the memory chip at an external connection terminal side. An array of resistor devices is provided on the second surface and along the array of connection pads at the opposite side of the memory chip. Plugs outside near-memory-chip ends of the external connection terminals penetrate the first and surfaces. A first wiring passes outside the array of resistor devices and the array of connection pads on the second surface, and connects one resistor device and one plug. A second wiring on the first surface connects one plug and one external connection terminal.Type: GrantFiled: September 21, 2010Date of Patent: February 19, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Taku Nishiyama
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Patent number: 8288855Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.Type: GrantFiled: November 3, 2011Date of Patent: October 16, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Naohisa Okumura, Kiyokazu Okada
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Publication number: 20120241933Abstract: In an embodiment, a semiconductor memory card includes a lead frame including external connection terminals, a lead portion, a chip component mounting portion and a semiconductor chip mounting portion, a chip component mounted on the chip component mounting portion, a memory chip disposed on the semiconductor chip mounting portion, and a controller chip. A rewiring layer is formed on a surface of the memory chip. The lead frame is resin-sealed. An electric circuit of the controller chip and the memory chip on the lead frame is formed by the lead portion, the rewiring layer and a metal wire connected to electrode pad of the chips, the lead portion, and the rewiring layer.Type: ApplicationFiled: February 29, 2012Publication date: September 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kazuhide Doi, Naohisa Okumura, Taku Nishiyama, Katsuyoshi Watanabe, Takeshi Ikuta
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Patent number: 8274141Abstract: A semiconductor memory card includes a wiring board having an outer shape where a cut-out portion is provided at a first long-edge. A second surface of the wiring board includes connection pads disposed along a portion except the cut-out portion of the first long-edge. A memory device is mounted on the second surface of the wiring board. The memory device includes electrode pads arranged along a long-edge positioning in a vicinity of the first long-edge of the wiring board, and one-sidedly disposed so as to correspond to disposed positions of the connection pads. A controller device is stacked on the memory device.Type: GrantFiled: March 9, 2009Date of Patent: September 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Tetsuya Yamamoto, Naohisa Okumura, Takuya Futatsuyama
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Publication number: 20120049378Abstract: According to one embodiment, a semiconductor storage device includes a plate and an external connection terminal. The plate is molded in a resin mold section. A semiconductor memory chip is placed on the plate. The external connection terminal is exposed to the outer circumferential surface of the semiconductor storage device. The plate includes a plurality of exposed portions exposed to the outer circumferential surface of the resin mold section. The plurality of exposed portions is electrically insulated from each other inside the resin mold section.Type: ApplicationFiled: March 18, 2011Publication date: March 1, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Junichi Asada, Taku Nishiyama, Atsuko Seki
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Publication number: 20120043671Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.Type: ApplicationFiled: November 3, 2011Publication date: February 23, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taku NISHIYAMA, Naohisa Okumura, Kiyokazu Okada
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Patent number: 8110434Abstract: A circuit board has a curved portion provided in at least one side of an external shape thereof. An external connecting terminal is provided on a first main surface of the circuit board. A semiconductor element is mounted on a second main surface of the circuit board. A first wiring network is provided in a region except the terminal region on the first main surface. A second wiring network is provided on the second main surface. Distance from the side including the curved portion to the first wiring network is larger than distance from at least one of the other sides to the first wiring networks, and distance from the side including the curved portion to the second wiring network is larger than distance from at least one of the other sides to the second wiring networks.Type: GrantFiled: January 25, 2010Date of Patent: February 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Okada, Kiyokazu Okada, Akinori Ono, Taku Nishiyama
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Publication number: 20110316134Abstract: According to the embodiment, a semiconductor storage device includes an organic substrate, a semiconductor memory chip, a lead frame, and a resin mold section. The lead frame includes an adhering portion. The organic substrate is singulated to have a shape in which a portion in which the organic substrate does not overlap with the placing portion is larger than a portion in which the organic substrate overlaps with the placing portion, in plan view. The lead frame further includes a first extending portion in the adhering portion that extends to a surface different from a surface of the resin mold section on a side of an insertion direction.Type: ApplicationFiled: June 24, 2011Publication date: December 29, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Hitoshi ISHII, Naohisa Okumura, Taku Nishiyama
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Patent number: 8080868Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.Type: GrantFiled: November 4, 2010Date of Patent: December 20, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Naohisa Okumura, Kiyokazu Okada
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Patent number: 8064206Abstract: A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.Type: GrantFiled: January 20, 2011Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Kiyokazu Okada, Yoriyasu Ando, Tetsuya Yamamoto, Naohisa Okumura
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Publication number: 20110254175Abstract: A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element gType: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taku NISHIYAMA, Tetsuya YAMAMOTO, Naohisa OKUMURA
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Patent number: 8004071Abstract: A semiconductor memory device includes: a wiring board including an element mounting portion and connection pads; a first element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the element mounting portion of the wiring board in a way that pad arrangement sides of the semiconductor elements face in the same direction, and that the electrode pads are exposed; a second element group including a plurality of semiconductor elements each having electrode pads arranged along one of outer sides of the semiconductor element, the plurality of semiconductor elements being layered stepwise on the first element group in a way that pad arrangement sides of the semiconductor elements face in the same direction as that of the first element group, and that the electrode pads are exposed, the second element group being disposed to be offset from the first element gType: GrantFiled: December 24, 2008Date of Patent: August 23, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Tetsuya Yamamoto, Naohisa Okumura
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Publication number: 20110115100Abstract: According to one embodiment, a semiconductor device includes a base, a memory chip, a controller chip, and a plurality of passive components. The base includes a bonding pad. The memory chip is provided above the base and connected to the bonding pad by a wire. Data can be electrically stored in the memory chip. The controller chip is provided in a memory area including the memory chip in a direction from the memory chip toward the base and controls an operation of the memory chip. The passive components are provided in the memory area.Type: ApplicationFiled: November 17, 2010Publication date: May 19, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naohisa OKUMURA, Taku NISHIYAMA
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Patent number: 7944037Abstract: A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements.Type: GrantFiled: April 19, 2010Date of Patent: May 17, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Tetsuya Yamamoto, Kiyokazu Okada
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Publication number: 20110110053Abstract: A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.Type: ApplicationFiled: January 20, 2011Publication date: May 12, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Kiyokazu Okada, Yoriyasu Ando, Tetsuya Yamamoto, Naohisa Okumura
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Publication number: 20110101110Abstract: According to one embodiment, a semiconductor device includes a memory chip and a controller chip. A circuit board includes a first surface on which an array of external connection terminals are provided and an second surface on which the memory and controller chips are provided. An array of connection pads is provided on the second surface and outside the memory chip at an external connection terminal side. An array of resistor devices is provided on the second surface and along the array of connection pads at the opposite side of the memory chip. Plugs outside near-memory-chip ends of the external connection terminals penetrate the first and surfaces. A first wiring passes outside the array of resistor devices and the array of connection pads on the second surface, and connects one resistor device and one plug. A second wiring on the first surface connects one plug and one external connection terminal.Type: ApplicationFiled: September 21, 2010Publication date: May 5, 2011Inventor: Taku NISHIYAMA
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Patent number: 7898813Abstract: A semiconductor memory device is provided with a wiring board which includes an element mounting portion and connection pads. Plural semiconductor memory elements are stacked on the element mounting portion of the wiring board. The semiconductor memory element of a lower side has a thickness greater than that of the semiconductor memory element of an upper side. The semiconductor memory elements are electrically connected to the connection pads of the wiring board via metal wires.Type: GrantFiled: June 25, 2007Date of Patent: March 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Kiyokazu Okada, Yoriyasu Ando, Tetsuya Yamamoto, Naohisa Okumura
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Publication number: 20110042467Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.Type: ApplicationFiled: November 4, 2010Publication date: February 24, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taku NISHIYAMA, Naohisa Okumura, Kiyokazu Okada
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Patent number: 7855446Abstract: A semiconductor memory card includes a wiring board which has a first pad region along a first long side and a second pad region along a second long side. First memory chips which configure a first chip group are stacked in a step-like shape on the wiring board. Second memory chips which configure a second chip group are stacked in a step-like shape on the first chip group with the direction reversed. The electrode pads of the first memory chips are electrically connected to the connection pads arranged on the first pad region, and the electrode pads of the second memory chips are electrically connected to the connection pads arranged on the second pad region.Type: GrantFiled: September 14, 2009Date of Patent: December 21, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Taku Nishiyama, Naohisa Okumura, Kiyokazu Okada
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Publication number: 20100200976Abstract: A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements.Type: ApplicationFiled: April 19, 2010Publication date: August 12, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taku NISHIYAMA, Tetsuya YAMAMOTO, Kiyokazu OKADA