Patents by Inventor Takuichiro Nakazawa
Takuichiro Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150253832Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: ApplicationFiled: May 22, 2015Publication date: September 10, 2015Inventors: Junichi NISHIMOTO, Takuichiro NAKAZAWA, Koji YAMADA, Toshihiro HATTORI
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Patent number: 9069911Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: GrantFiled: July 9, 2014Date of Patent: June 30, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Publication number: 20140325093Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: ApplicationFiled: July 9, 2014Publication date: October 30, 2014Inventors: Junichi NISHIMOTO, Takuichiro NAKAZAWA, Koji YAMADA, Toshihiro HATTORI
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Patent number: 8812750Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: GrantFiled: October 18, 2013Date of Patent: August 19, 2014Assignee: Renesas Electronics CorporationInventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Publication number: 20140053010Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: ApplicationFiled: October 18, 2013Publication date: February 20, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Junichi NISHIMOTO, Takuichiro NAKAZAWA, Koji YAMADA, Toshihiro HATTORI
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Patent number: 8595388Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: GrantFiled: July 23, 2012Date of Patent: November 26, 2013Assignee: Renesas Electronics CorporationInventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Publication number: 20120290743Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: ApplicationFiled: July 23, 2012Publication date: November 15, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Junichi NISHIMOTO, Takuichiro NAKAZAWA, Koji YAMADA, Toshihiro HATTORI
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Patent number: 8244926Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: GrantFiled: February 11, 2011Date of Patent: August 14, 2012Assignee: Renesas Electronics CorporationInventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Patent number: 7975077Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: GrantFiled: May 22, 2009Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Publication number: 20110131349Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: ApplicationFiled: February 11, 2011Publication date: June 2, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Patent number: 7725616Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: GrantFiled: June 4, 2008Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Publication number: 20090235007Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: ApplicationFiled: May 22, 2009Publication date: September 17, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Publication number: 20080250187Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: ApplicationFiled: June 4, 2008Publication date: October 9, 2008Inventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Patent number: 7401165Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: GrantFiled: August 15, 2005Date of Patent: July 15, 2008Assignee: Renesas Technology CorporationInventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Patent number: 7401163Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: GrantFiled: October 24, 2001Date of Patent: July 15, 2008Assignee: Renesas Technology CorporationInventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Publication number: 20050273526Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: ApplicationFiled: August 15, 2005Publication date: December 8, 2005Inventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Patent number: 6819334Abstract: An information processing apparatus has a processing unit, a memory unit for storing display data processed by the processing unit, a display image rotation engine which is coupled with a buffer memory to sequentially transfer display data to the buffer memory and which responds to a command of predetermined timing for display data update to store the display data stored in the memory unit in read sequence different from write sequence, a display controller for delivering the display data, stored in the buffer memory, in the memory unit by means of the rotation engine to a display device, and a bus for mutually coupling the processing unit, the memory unit, the display controller and the rotation engine.Type: GrantFiled: March 3, 2000Date of Patent: November 16, 2004Assignee: Hitachi, Ltd.Inventors: Toru Owada, Isao Takita, Yasushi Nagai, Kanetoshi Saito, Takuichiro Nakazawa
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Publication number: 20040064746Abstract: One data processor (101) is provided with an interface means (119) for realizing connection with the other data processor (100), this interface means is provided with a function for connecting the other data processor as a bus master to an internal bus (108) of one data processor, and the relevant other data processor is capable of operating in direct peripheral functions memory mapped to the internal bus from an external side via said interface means. Accordingly, the data processor can utilize the peripheral functions of the other data processor without intermission of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.Type: ApplicationFiled: July 31, 2003Publication date: April 1, 2004Inventors: Junichi Nishimoto, Takuichiro Nakazawa, Koji Yamada, Toshihiro Hattori
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Data processing system having apparatus for increasing the execution speed of bit field instructions
Patent number: 5210835Abstract: In addition to an ordinary bit field instruction without limitation which makes use of an offset value and a field width, a bit field instruction with limitation which does not calculate the spread of the bit field is separately installed. In the present invention the calculation for determination of the spread of the bit field is not performed when the bit field instruction with limitation is executed. In addition, when executing a bit field instruction with limitation, the offset value and the field width can be obtained directly as immediate values thereby decreasing the execution time of the instruction.Type: GrantFiled: January 2, 1990Date of Patent: May 11, 1993Assignees: Ken Sakamura, Hitachi, Ltd., Hitachi Microcomputer Engineering Co., Ltd.Inventors: Ken Sakamura, Takuichiro Nakazawa, Atsushi Hasegawa, Ikuya Kawasaki, Kazuhiko Iwasaki -
Patent number: 5125095Abstract: A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.Type: GrantFiled: March 28, 1991Date of Patent: June 23, 1992Assignees: Hitachi Microcomputer Engineering Ltd., Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Takuichiro Nakazawa, Makoto Hanawa, Atsushi Hasegawa, Ikuya Kawasaki, Kazuhiko Iwasaki, Shigeki Morinaga, Hisashi Kaziwara, Takeshi Asai, Junichi Tatezaki