Abstract: In addition to an ordinary bit field instruction without limitation which makes use of an offset value and a field width, a bit field instruction with limitation which does not calculate the spread of the bit field is separately installed. In the present invention the calculation for determination of the spread of the bit field is not performed when the bit field instruction with limitation is executed. In addition, when executing a bit field instruction with limitation, the offset value and the field width can be obtained directly as immediate values thereby decreasing the execution time of the instruction.

Abstract: A content-addressable memory which has a storage bit cell (121, 122), signal supplying circuits (380, 390, 400) and comparison circuits (125, 126, 127, 128). The storage bit cell (121, 122) holds a first data (D) and a second data (D) of opposite phases. The signal supplying circuits (380, 390, 400) supply a first signal (a1) and a second signal (a1), respectively, to a first data line (180) and a second data line (190) of the storage bit cell (121, 122) in response to an input signal (A1) and a control signal (510). The first and second signals (a1, a1) are in opposite phases.