Abstract: There is provided a method of modulating a data bit series consisting of a first value (e.g., 1) and a second value (e.g., 0) whereby a transition as a state transition is caused so as to satisfy the following conditions of (a) to (d).(a) The transition at the boundary portion of the bit cell which is sandwiched by bits 0.(b) The transition at the central portion of the bit cell of bit 1.(c) Among an even number of the bits of 1 which are sandwiched by bits 0, the transition is inhibited at the central portion of each bit cell of the last two bits of 1 and the transition is caused at the boundary portion of these two bit cells of 1.(d) When at least one bit in a pattern which starts from the two bits of (01) appears at a location next to an even number of the bits of 1 subsequent to bit of 0, the transition is caused at the central portion of the bit cell of bit 0 between these two bits.