Patents by Inventor Takuji Tanaka
Takuji Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240097441Abstract: A management system includes a plurality of resources configured to be electrically connected to an external power supply, and a management device configured to manage the resources. The management device includes a planning unit and a management unit. The planning unit is configured to determine a power balancing plan of each of the resources by using first information on a use schedule of each of the resources and second information indicating a magnitude of an environmental load in a process of generating electric power to be supplied by the external power supply. The management unit is configured to manage the resources to cause each of the resources to operate according to the power balancing plan or a modified power balancing plan in power balancing of the external power supply.Type: ApplicationFiled: August 3, 2023Publication date: March 21, 2024Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, CHUBU ELECTRIC POWER MIRAIZ CO., INC., CHUBU ELECTRIC POWER CO., INC.Inventors: Yusuke HORII, Eiko Megan UCHIDA, Masashi TANAKA, Masato EHARA, Sachio TOYORA, Tomoya TAKAHASHI, Akinori MORISHIMA, Takuji MATSUBARA, Tohru NAKAMURA, Ryou TAKAHASHI, Kenta ITO, Toshiki SUZUKI, Atsushi MIYASHITA, Takashi OCHIAI
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Patent number: 11937495Abstract: An organic light-emitting device containing both a compound represented by the following general formula (1) and a compound represented by the following general formula (2) has a high light emission efficiency. The rings a to c each are a benzene ring that can be optionally condensed, R1 and R2 each represent a substituted or unsubstituted aryl group, etc., four of R31 to R35 each are a substituted or unsubstituted carbazol-9-yl group, but all of these four are not the same, and the remaining one is a hydrogen atom, a cyano group, etc.Type: GrantFiled: August 7, 2019Date of Patent: March 19, 2024Assignees: KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION, KWANSEI GAKUIN EDUCATIONAL FOUNDATION, KYULUX, INC.Inventors: Hajime Nakanotani, Takuji Hatakeyama, Yasuhiro Kondo, Yasuyuki Sasada, Motoki Yanai, Chin-Yiu Chan, Masaki Tanaka, Hiroki Noda, Chihaya Adachi, Yoshitake Suzuki, Naoto Notsuka
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Publication number: 20240067189Abstract: Included are: a surrounding situation acquiring unit that acquires surrounding situation information regarding a situation around a control target apparatus; a control amount inferring unit that infers a control amount of the control target apparatus on the basis of the surrounding situation information and acquires attention-paid region information regarding an attention-paid region in the surrounding situation information used when the control amount is inferred; a target detecting unit that detects a position of a target present around the control target apparatus on the basis of the surrounding situation information acquired by the surrounding situation acquiring unit; and a reliability determining unit that determines reliability of the control amount inferred by the control amount inferring unit on the basis of the attention-paid region information acquired by the control amount inferring unit and target position information regarding the position of the target detected by the target detecting unit.Type: ApplicationFiled: March 22, 2021Publication date: February 29, 2024Applicant: Mitsubishi Electric CorporationInventors: Takumi SATO, Takuji MORIMOTO, Genki TANAKA
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Patent number: 8789002Abstract: A method of manufacturing a semiconductor device on the basis of changed design layout data. The method decides a functional relationship between layout parameters based on layout data and the electrical characteristic of a plurality of semiconductor elements. Candidates of the values of the layout parameters are extracted from design layout data so as to decrease the difference between a target electrical characteristic and a predicted electrical characteristic. A specific value from the candidate values of the layout parameters is selected and the design layout data is changed based on the specific selected value.Type: GrantFiled: December 19, 2008Date of Patent: July 22, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Takuji Tanaka
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Publication number: 20130316417Abstract: The present application includes a process and a microorganism of the genus Lactobacillus that converts glycerol to 1,3-propanediol. The conversion is accomplished by a proprietary microorganism that is easily cultured in glycerol rich waste products of ethanol production, such as thin stillage.Type: ApplicationFiled: October 7, 2011Publication date: November 28, 2013Applicant: University of SaskatchewanInventors: Martin J.T. Reaney, Monique Haakensen, Darren Korber, Takuji Tanaka, Kornsulee Ratanapariyanuch
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Patent number: 8227329Abstract: A method for manufacturing a semiconductor device includes steps of preparing a semiconductor substrate having a first conductive type; implanting a first impurity having the first conductive type in the semiconductor substrate to form a well region having a bottom portion; and implanting a second impurity having a second conductive type in the semiconductor substrate to form an impurity region having a top portion, the top of the impurity region being in contact with the bottom portion of the well region. Implantation of the second impurity includes a first step of implanting the second impurity and a second step of implanting the second impurity, wherein a first implantation area of the first step of implanting the second impurity being broader or narrower than a second implantation area of the second step of implanting the second impurity.Type: GrantFiled: November 28, 2011Date of Patent: July 24, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Takuji Tanaka
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Publication number: 20120070969Abstract: A method for manufacturing a semiconductor device includes steps of preparing a semiconductor substrate having a first conductive type; implanting a first impurity having the first conductive type in the semiconductor substrate to form a well region having a bottom portion; and implanting a second impurity having a second conductive type in the semiconductor substrate to form an impurity region having a top portion, the top of the impurity region being in contact with the bottom portion of the well region. Implantation of the second impurity includes a first step of implanting the second impurity and a second step of implanting the second impurity, wherein a first implantation area of the first step of implanting the second impurity being broader or narrower than a second implantation area of the second step of implanting the second impurity.Type: ApplicationFiled: November 28, 2011Publication date: March 22, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Takuji Tanaka
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Patent number: 8130529Abstract: A semiconductor device has a pair of gate electrodes extending adjacent to and non-parallel to each other, a source and/or drain region located between the pair of gate electrodes for forming a pair of transistors with the gate electrodes, and a contact electrode disposed between the pair of gate electrodes in contact with the source and/or drain region in a contact area so that the center of the contact area is shifted from the center of the source and/or drain region in a direction along which the distance between the pair of gate electrodes becomes greater.Type: GrantFiled: November 19, 2008Date of Patent: March 6, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Takuji Tanaka
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Patent number: 8084341Abstract: The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed.Type: GrantFiled: December 18, 2009Date of Patent: December 27, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Takuji Tanaka
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Patent number: 8084844Abstract: A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the p-type Si substrate so that it surrounds the p-type well region. A plurality of conductive regions which pierce through the n-type well region are formed at regular intervals. By doing so, parasitic resistance from the p-type Si substrate, through the plurality of conductive regions, to the n-type MOS transistors becomes low. Accordingly, when back bias is applied to a contact region, the back bias potential of the n-type MOS transistors can be controlled uniformly. As a result, the influence of noise from the p-type Si substrate or the p-type well region can be reduced.Type: GrantFiled: July 16, 2009Date of Patent: December 27, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Takuji Tanaka
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Patent number: 8026577Abstract: A semiconductor apparatus according to the present invention includes a first well-region and a second well-region in a semiconductor substrate, and a plurality of transistors formed to the second well-region. Further, the semiconductor apparatus includes a through-hole region that is formed so as to pierce through the first well-region and enables the second well-region to be electrically conductive to the semiconductor substrate on the bottom of the second well. Furthermore, in the semiconductor apparatus, the border of the through-hole region is arranged between the transistors, and is also arranged to be planarity apart from the transistor.Type: GrantFiled: February 13, 2008Date of Patent: September 27, 2011Assignee: Fujitsu Semiconductor LimitedInventor: Takuji Tanaka
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Patent number: 7852655Abstract: Disclosed is a semiconductor memory device capable of realizing reduction in an SRAM unit cell area. Using as a standard configuration a parallel-type SRAM unit cell having each pair of load transistors, driver transistors and transfer transistors, all or a part of the gate electrodes and active regions configuring at least any one of the pairs of the transistors, for example, the pair of the transfer transistors are configured obliquely in a predetermined direction from the standard configuration. As a result, a size in a cell outside part including the driver transistor and the transfer transistor is reduced. At the same time, a distance between the load transistors in the central part is reduced as compared with that in the standard configuration. Thus, area reduction in the whole SRAM unit cell is realized.Type: GrantFiled: August 9, 2007Date of Patent: December 14, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Takuji Tanaka
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Publication number: 20100093163Abstract: The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed.Type: ApplicationFiled: December 18, 2009Publication date: April 15, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Takuji TANAKA
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Patent number: 7659188Abstract: The present invention provides a method for manufacturing a semiconductor device which includes a step of forming one optional impurity region in a semiconductor substrate at a place apart from the surface thereof, and in the method described above, ion implantation is performed a plurality of times while the position of an end portion of a mask pattern used for ion implantation is changed.Type: GrantFiled: April 6, 2006Date of Patent: February 9, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Takuji Tanaka
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Publication number: 20090273039Abstract: A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well region is formed in the p-type Si substrate so that it surrounds the p-type well region. A plurality of conductive regions which pierce through the n-type well region are formed at regular intervals. By doing so, parasitic resistance from the p-type Si substrate, through the plurality of conductive regions, to the n-type MOS transistors becomes low. Accordingly, when back bias is applied to a contact region, the back bias potential of the n-type MOS transistors can be controlled uniformly. As a result, the influence of noise from the p-type Si substrate or the p-type well region can be reduced.Type: ApplicationFiled: July 16, 2009Publication date: November 5, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Takuji TANAKA
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Patent number: 7579246Abstract: An active region and an opposite conductivity active region are formed in a semiconductor substrate. The opposite conductivity active region is covered with a resist pattern. Impurities are implanted into a surface layer of the active region. An angle ?0 is defined as a tilt angle obtained by tilting a virtual plane perpendicular to the substrate and including an edge of the active region, toward the resist pattern by using as a fulcrum a point on the substrate nearest to the resist pattern, until the virtual plane contacts the resist pattern. The ion implantation is performed in a direction having a tilt angle larger than ?0 and allowing ions passed through the uppermost edge of the resist pattern to be incident upon an area between the resist pattern and the active region, and is not performed along a direction allowing the ions to be incident upon the active region.Type: GrantFiled: September 22, 2006Date of Patent: August 25, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Takuji Tanaka
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Publication number: 20090172611Abstract: Manufacturing a semiconductor device by measuring an electrical characteristic of a plurality of semiconductor elements, defining layout parameters on the basis of layout data and deciding a functional relationship between the layout parameters and the electrical characteristic, extracting values of the layout parameters from design layout data of the semiconductor device, calculating a predicted electrical characteristic of the semiconductor device, calculating a difference between a target electrical characteristic and the predicted electrical characteristic of the semiconductor device, generating a plurality of candidates of the values of the layout parameters, selecting a specific value from among the candidates so as to decrease the difference between the target electrical characteristic and the predicted electrical characteristic, changing the design layout data on the basis of the specific value, and manufacturing the semiconductor device on the basis of the changed design layout data.Type: ApplicationFiled: December 19, 2008Publication date: July 2, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Takuji Tanaka
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Publication number: 20090134473Abstract: A semiconductor device has a pair of gate electrodes extending adjacent to and non-parallel to each other, a source and/or drain region located between the pair of gate electrodes for forming a pair of transistors with the gate electrodes, and a contact electrode disposed between the pair of gate electrodes in contact with the source and/or drain region in a contact area so that the center of the contact area is shifted from the center of the source and/or drain region in a direction along which the distance between the pair of gate electrodes becomes greater.Type: ApplicationFiled: November 19, 2008Publication date: May 28, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Takuji TANAKA
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Publication number: 20080150032Abstract: A semiconductor apparatus according to the present invention includes a first well-region and a second well-region in a semiconductor substrate, and a plurality of transistors formed to the second well-region. Further, the semiconductor apparatus includes a through-hole region that is formed so as to pierce through the first well-region and enables the second well-region to be electrically conductive to the semiconductor substrate on the bottom of the second well. Furthermore, in the semiconductor apparatus, the border of the through-hole region is arranged between the transistors, and is also arranged to be planarity apart from the transistor.Type: ApplicationFiled: February 13, 2008Publication date: June 26, 2008Applicant: FUJITSU LIMITEDInventor: Takuji Tanaka
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Publication number: 20080037311Abstract: Disclosed is a semiconductor memory device capable of realizing reduction in an SRAM unit cell area. Using as a standard configuration a parallel-type SRAM unit cell having each pair of load transistors, driver transistors and transfer transistors, all or a part of the gate electrodes and active regions configuring at least any one of the pairs of the transistors, for example, the pair of the transfer transistors are configured obliquely in a predetermined direction from the standard configuration. As a result, a size in a cell outside part including the driver transistor and the transfer transistor is reduced. At the same time, a distance between the load transistors in the central part is reduced as compared with that in the standard configuration. Thus, area reduction in the whole SRAM unit cell is realized.Type: ApplicationFiled: August 9, 2007Publication date: February 14, 2008Applicant: FUJITSU LIMITEDInventor: Takuji TANAKA