Patents by Inventor Takuji Yoshida

Takuji Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110102242
    Abstract: The present invention includes a transmitter/receiver 20 that transmits/receives an FMCW based sweep signal, a velocity grouping unit 36 that performs grouping of a target for each velocity range by a velocity of the target calculated based on the sweep signal from the transmitter/receiver, and a correlation tracking unit 37 that performs correlation tracking for each velocity group which is grouped by the velocity grouping unit.
    Type: Application
    Filed: March 19, 2010
    Publication date: May 5, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Takeya, Kazuaki Kawabata, Kazuki Oosuga, Takuji Yoshida, Tomohiro Yoshida, Masato Niwa, Hideto Goto
  • Publication number: 20100142015
    Abstract: A hologram recording film manufacturing method includes the steps of obtaining a laminated structure by alternately laminating M (where M?2) photosensitive material precursor layers including a photosensitive material and at least one (M?1) resin layer on one another, obtaining M photosensitive material layers, where at least two interference fringes with a desired pitch and a desired slant angle are formed on each of the M photosensitive material layers, from the M photosensitive material precursor layers by irradiating the laminated structure with a reference laser light beam and an object laser light beam, and making the slant angles of the M photosensitive material layers different from each other while retaining the pitch value, which is defined on a face of the photosensitive material layer, by irradiating the laminated structure with an energy ray from the laminated structure's one face side, and heating the laminated structure.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 10, 2010
    Applicant: SONY CORPORATION
    Inventors: Mieko Kuwahara, Takuji Yoshida, Katsuyuki Akutsu
  • Patent number: 7733446
    Abstract: The present invention intends to provide a manufacturing method of a semi-transmissive liquid crystal display device in which method a structure and manufacturing process thereof are simplified to enable to reduce the manufacturing cost. In order to achieve the above object, a semi-transmissive liquid crystal display device in the invention has a layer constitution in which a reflective pixel electrode is formed with a second conductive film that constitutes a source electrode, a drain electrode, a source wiring and so on and on an upper layer of the second metal film a transmissive pixel electrode made of a transparent conductive film is formed through the insulating film. A TFT array substrate can be formed through 5 times of photoengraving process.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: June 8, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yuichi Masutani, Shingo Nagano, Takuji Yoshida, Nobuaki Ishiga, Kazunori Inoue
  • Patent number: 7470571
    Abstract: A method of producing a thin film transistor array substrate which includes an insulating substrate, a display pixel having a pixel electrode connected to a drain electrode, a gate wiring, and a source wiring perpendicular to the gate wiring, comprising forming a first thin metal multi-layer film an upper layer of which includes aluminum, and spreading a photo-resist, forming the photo-resist to a thickness less in an area connected to a second thin metal film than other area, patterning the first thin metal film, reducing a thickness of the photo-resist layer and removing the photo-resist in the area, removing the upper layer in the area to expose a lower layer, forming an interlayer insulating film and patterning it to expose the lower layer in the area, and patterning the second thin metal film to include the area, to connect the lower layer to the second thin metal film.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: December 30, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuaki Ishiga, Takuji Yoshida, Yuichi Masutani, Shingo Nagano
  • Patent number: 7415170
    Abstract: A data processing apparatus is provided for processing an image signal obtained from a solid-state image pickup device, in which a plurality of types of color filters are discretely provided on pixels, and a pixel to be interpolated and surrounding pixels thereof have image signals. The apparatus comprises an interpolation section for generating a missing color signal in the image signal of each pixel by interpolation using at least the image signals of the surrounding pixels among the image signals of the pixel to be interpolated and the surrounding pixels thereof. The interpolation section obtains an interpolation pattern, which is similar to a pattern of data values of the pixel to be interpolated and the surrounding pixels thereof, depending on uniformity and gradient of the image signals of the pixel to be interpolated and the surrounding pixels thereof, and performs interpolation depending on the interpolation pattern.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: August 19, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuji Kimura, Takuji Yoshida
  • Publication number: 20080138921
    Abstract: A liquid crystal apparatus includes a TFT array substrate which includes gate wirings having a gate electrode, source wirings having a source electrode, a thin film transistor having the gate electrode, a semiconductor layer, the source electrode, and a drain electrode, an interlayer insulating film provided above the thin film transistor and the gate and source wirings, a transparent pixel electrode having a first transparent conductive film connected to the drain electrode through a contact hole, and put into contact with a surface of a insulating substrate through a pixel opening provided in a gate insulating film and the interlayer insulating film, a reflective pixel electrode made of an Al-alloy connected to the drain electrode, and a second transparent conductive film formed on the reflective electrode. The second transparent conductive film has a same pattern shape as the reflective pixel electrode and a thickness thereof is at least 5 nm.
    Type: Application
    Filed: February 11, 2008
    Publication date: June 12, 2008
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tadaki Nakahori, Nobuaki Ishiga, Kensuke Nagayama, Takuji Yoshida
  • Publication number: 20080118996
    Abstract: A method of producing a thin film transistor array substrate which includes an insulating substrate, a display pixel having a pixel electrode connected to a drain electrode, a gate wiring, and a source wiring perpendicular to the gate wiring, comprising forming a first thin metal multi-layer film an upper layer of which includes aluminum, and spreading a photo-resist, forming the photo-resist to a thickness less in an area connected to a second thin metal film than other area, patterning the first thin metal film, reducing a thickness of the photo-resist layer and removing the photo-resist in the area, removing the upper layer in the area to expose a lower layer, forming an interlayer insulating film and patterning it to expose the lower layer in the area, and patterning the second thin metal film to include the area, to connect the lower layer to the second thin metal film.
    Type: Application
    Filed: December 6, 2007
    Publication date: May 22, 2008
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Nobuaki Ishiga, Takuji Yoshida, Yuichi Masutani, Shingo Nagano
  • Patent number: 7352421
    Abstract: A liquid crystal apparatus includes a TFT array substrate which includes gate wirings having a gate electrode, source wirings having a source electrode, a thin film transistor having the gate electrode, a semiconductor layer, the source electrode, and a drain electrode, an interlayer insulating film provided above the thin film transistor and the gate and source wirings, a transparent pixel electrode having a first transparent conductive film connected to the drain electrode through a contact hole, and put into contact with a surface of a insulating substrate through a pixel opening provided in a gate insulating film and the interlayer insulating film, a reflective pixel electrode made of an Al-alloy connected to the drain electrode, and a second transparent conductive film formed on the reflective electrode. The second transparent conductive film has a same pattern shape as the reflective pixel electrode and a thickness thereof is at least 5 nm.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: April 1, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tadaki Nakahori, Nobuaki Ishiga, Kensuke Nagayama, Takuji Yoshida
  • Patent number: 7323713
    Abstract: A method of producing a thin film transistor array substrate which includes an insulating substrate, a display pixel having a pixel electrode connected to a drain electrode, a gate wiring, and a source wiring perpendicular to the gate wiring, comprising forming a first thin metal multi-layer film an upper layer of which includes aluminum, and spreading a photo-resist, forming the photo-resist to a thickness less in an area connected to a second thin metal film than other area, patterning the first thin metal film, reducing a thickness of the photo-resist layer and removing the photo-resist in the area, removing the upper layer in the area to expose a lower layer, forming an interlayer insulating film and patterning it to expose the lower layer in the area, and patterning the second thin metal film to include the area, to connect the lower layer to the second thin metal film.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: January 29, 2008
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuaki Ishiga, Takuji Yoshida, Yuichi Masutani, Shingo Nagano
  • Patent number: 7228007
    Abstract: A resolution correction apparatus of the present invention includes: an outline signal generator for generating an outline signal, which represents an outline of an image, based on an image signal; an outline correction signal generator for generating an outline correction signal to emphasize the outline of the image, based on the outline signal generated by the outline signal generator and an amount of correction which is increased along radial directions from the center of the image to peripheral portions thereof; and an outline correction signal adder for adding the outline correction signal generated by the outline correction signal generator to the image signal.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: June 5, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Takuji Yoshida
  • Publication number: 20070026324
    Abstract: A substrate with a light-shielding film according to one mode of the invention is obtained in a method of manufacture of a substrate with a light-shielding film having a light-shielding film pattern formed on a substrate, by depositing in order a first film having chromium oxide and a second film having chromium on a substrate, to form a multilayer film; forming a resist pattern on the multilayer film; performing etching of the multilayer film, using an etching liquid comprising ceric ammonium nitrate to which nitric acid is added at a concentration of at least 2.5 mol/liter, to form a light-shielding film pattern; and removing the resist pattern.
    Type: Application
    Filed: July 12, 2006
    Publication date: February 1, 2007
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takuji Yoshida, Hatsumi Kimura, Nobuaki Ishiga, Takahito Yamabe, Toshio Araki
  • Patent number: 7164439
    Abstract: A flicker correction apparatus for correcting a flicker component of an image signal obtained by imaging an object using an imaging device is provided. The apparatus comprises an image average calculation section for calculating an average of the image signal, a flicker frequency calculation section for calculating a flicker frequency, a flicker data extraction section for extracting flicker data using the average of the image signal and the flicker frequency, a flicker determination section for determining the presence or absence of a flicker phenomenon using the flicker data, a flicker correction amount calculation section for calculating a flicker correction amount using the flicker data, and a flicker correction section for removing the flicker component of the image data using the flicker correction amount.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: January 16, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takuji Yoshida, Katsuji Kimura, Noboru Kubo, Hiroyuki Okuhata, Toshiyuki Kaya, Shinsuke Hamanaka, Eiji Ono, Isao Shirakawa
  • Publication number: 20060267120
    Abstract: A liquid crystal apparatus includes a TFT array substrate which includes gate wirings having a gate electrode, source wirings having a source electrode, a thin film transistor having the gate electrode, a semiconductor layer, the source electrode, and a drain electrode, an interlayer insulating film provided above the thin film transistor and the gate and source wirings, a transparent pixel electrode having a first transparent conductive film connected to the drain electrode through a contact hole, and put into contact with a surface of a insulating substrate through a pixel opening provided in a gate insulating film and the interlayer insulating film, a reflective pixel electrode made of an Al-alloy connected to the drain electrode, and a second transparent conductive film formed on the reflective electrode. The second transparent conductive film has a same pattern shape as the reflective pixel electrode and a thickness thereof is at least 5 nm.
    Type: Application
    Filed: March 1, 2006
    Publication date: November 30, 2006
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Tadaki Nakahori, Nobuaki Ishiga, Kensuke Nagayama, Takuji Yoshida
  • Publication number: 20060189123
    Abstract: A fine wiring line profile with satisfactory precision is formed from a multilayer film containing a first layer made of an aluminum alloy and a second layer formed thereon made of a molybdenum-niobium alloy, by simultaneously etching the two layers constituting the multilayer film through only one etching operation while preventing the upper layer from forming overhangs. An etchant for etching a multilayer film containing an aluminum alloy layer formed over a substrate and a molybdenum-niobium alloy layer formed thereon having a niobium content of 2-19% by weight contains an aqueous solution of an acid mixture containing phosphoric acid, nitric acid, and an organic acid; and a method of etching is carried out with this etchant. The etchant preferably has a phosphoric acid concentration Np of 50-75% by weight, a nitric acid concentration Nn of 2-15% by weight, and an acid ingredient concentration defined by Np+(98/63)Nn of 55-85% by weight.
    Type: Application
    Filed: November 30, 2005
    Publication date: August 24, 2006
    Applicants: ADVANCED DISPLAY INC., MITSUBISHI CHEMICAL CORPORATION
    Inventors: Noriyuki Saitou, Takuji Yoshida, Kazunori Inoue, Makoto Ishikawa, Yoshio Kamiharaguchi
  • Patent number: 7084017
    Abstract: A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The second metallic pattern is surrounded by the semiconductor pattern.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: August 1, 2006
    Assignee: Advanced Display Inc.
    Inventors: Nobuhiro Nakamura, Kazunori Inoue, Takuji Yoshida, Kazuhiro Kobayashi, Ken Nakashima
  • Patent number: 7031197
    Abstract: An electrically erasable programmable read-only memory receives a single supply voltage and a ground voltage, and generates a first voltage higher than both the supply voltage and the ground voltage, and a second voltage lower than both the supply voltage and the ground voltage. Each memory cell in the memory has a nonvolatile storage transistor with a floating gate. To erase the memory cell, the first voltage is applied on a first side of the floating gate and th second voltage is on a second, opposite side of the floating gate. To program the memory cell, the second voltage is applied on the first side of the floating gate, and the first voltage is applied on the second side of the floating gate.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: April 18, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Takuji Yoshida
  • Publication number: 20060022199
    Abstract: A method of producing a thin film transistor array substrate which includes an insulating substrate, a display pixel having a pixel electrode connected to a drain electrode, a gate wiring, and a source wiring perpendicular to the gate wiring, comprising forming a first thin metal multi-layer film an upper layer of which includes aluminum, and spreading a photo-resist, forming the photo-resist to a thickness less in an area connected to a second thin metal film than other area, patterning the first thin metal film, reducing a thickness of the photo-resist layer and removing the photo-resist in the area, removing the upper layer in the area to expose a lower layer, forming an interlayer insulating film and patterning it to expose the lower layer in the area, and patterning the second thin metal film to include the area, to connect the lower layer to the second thin metal film.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 2, 2006
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Nobuaki Ishiga, Takuji Yoshida, Yuichi Masutani, Shingo Nagano
  • Publication number: 20050231616
    Abstract: In the DSP which processes an image pickup signal obtained via an optical lens (imaging optical system) and outputs the resulting image pickup signal as processes to an image display section, distortion aberration due to the optical lens is corrected according to a distance from a pixel position corresponding to an optical axis of the optical lens by changing the pixel position for each of a target image in radial directions when the pixel position corresponding to the optical axis is set as a center while suppressing an occurrence of jaggy in the resulting image. With this structure, an image pickup apparatus which corrects distortion aberration by changing pixel position only in radial directions from a pixel position corresponding to an optical axis of the imaging optical system while suppressing an occurrence of jaggy.
    Type: Application
    Filed: April 12, 2005
    Publication date: October 20, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yoshio Iwai, Katsuji Kimura, Takuji Yoshida
  • Publication number: 20050209446
    Abstract: A compound represented by the general formula (I) or a salt thereof which has excellent antibacterial activity (R1 represents hydrogen atom or an alkylcarbonyl group, R2 represents hydrogen atom, oxygen atom, hydroxyl group, or an alkylcarbonyloxy group, for example, when R2 is hydrogen atom, R3 represents group (a) (each of R5 and R6 represents hydrogen atom or an alkyl group), R4 represents hydrogen atom or group (c) (each of R8 and R9 represents hydrogen atom or an alkylcarbonyl group), and Me represents methyl group).
    Type: Application
    Filed: February 25, 2003
    Publication date: September 22, 2005
    Applicant: Meiji Seika Kaisha Ltd.
    Inventors: Tomoaki Miura, Ken-ichi Kurihara, Takuji Yoshida, Keiichi Ajito
  • Publication number: 20050082527
    Abstract: A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The second metallic pattern is surrounded by the semiconductor pattern.
    Type: Application
    Filed: October 27, 2004
    Publication date: April 21, 2005
    Applicant: ADVANCED DISPLAY INC.
    Inventors: Nobuhiro Nakamura, Kazunori Inoue, Takuji Yoshida, Kazuhiro Kobayashi, Ken Nakashima