Patents by Inventor Takumi Danjo

Takumi Danjo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140292410
    Abstract: A folded cascode amplifier circuit includes: an input stage having a pair of transistors and configured to output a positive phase intermediate signal and an opposite phase intermediate signal; a cascode amplification stage having pairs of transistors connected in multiple stages, to which the positive phase intermediate signal and the opposite phase intermediate signal are supplied, and which is configured to output a positive phase output signal and an opposite phase output signal, which are differential signals; a first capacitor connected between a signal line of the positive phase intermediate signal and a signal line of the opposite phase output signal; and a second capacitor connected between a signal line of the opposite phase intermediate signal and a signal line of the positive phase output signal.
    Type: Application
    Filed: February 12, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Takumi Danjo
  • Patent number: 8836376
    Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo
  • Patent number: 8760338
    Abstract: A comparator includes: a differential amplifier circuit to operate based on a clock signal and output a first intermediate output and a second intermediate output corresponding to a first input signal and a second input signal respectively; and a differential latch circuit to operate based on the clock signal and vary a state based on the first intermediate output and the second intermediate output, the differential latch circuit having a controllable sensitivity with respect to a state variation of the first intermediate output and the second intermediate output.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: June 24, 2014
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo
  • Publication number: 20140152482
    Abstract: A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value.
    Type: Application
    Filed: October 31, 2013
    Publication date: June 5, 2014
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Masanori HOSHINO, Takumi DANJO
  • Publication number: 20140132437
    Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.
    Type: Application
    Filed: August 28, 2013
    Publication date: May 15, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Takumi DANJO
  • Patent number: 8669895
    Abstract: Various embodiments of an analog-to-digital (A/D) device are described herein, with the A/D device using at least a comparison unit, a comparative operation control circuit, a delay circuit, and a successive operation control circuit arranged so as, it may, among other things, mitigate conversion errors that may be due to differences in properties of circuit elements therein. And the A/D device may be implemented in, among other things, a signal processing device.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: March 11, 2014
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo
  • Patent number: 8384571
    Abstract: An analog-to-digital conversion circuit includes: comparators to compare an input analog signal and one of reference voltages corresponding to each operation in an analog-to-digital conversion; an interpolating comparator to compare the input analog signal and a determination voltage between first and second reference voltages corresponding to two comparators; a correction value acquisition circuit to calculate a correction value to correct an error between the input analog signal and the determination voltage; a correction value application circuit to set the correction value in the interpolating comparator; a test voltage generation circuit to supply the two comparators with a first test voltage corresponding to one of the determination voltages; a common voltage generation circuit to supply the two comparators with a second test voltage; and a correction value calculation circuit to calculate respective correction values corresponding to the determination voltages based on errors corresponding to the first
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: February 26, 2013
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo
  • Patent number: 8339296
    Abstract: An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: December 25, 2012
    Assignee: Fujitsu Limited
    Inventor: Takumi Danjo
  • Publication number: 20120127007
    Abstract: A comparison circuit includes: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.
    Type: Application
    Filed: February 1, 2012
    Publication date: May 24, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Takumi Danjo, Takeshi Takayama, Sanroku Tsukamoto
  • Patent number: 8130130
    Abstract: A comparison circuit includes: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: March 6, 2012
    Assignee: Fujitsu Limited
    Inventors: Takumi Danjo, Takeshi Takayama, Sanroku Tsukamoto
  • Publication number: 20110309961
    Abstract: An analog-to-digital conversion circuit includes: comparators to compare an input analog signal and one of reference voltages corresponding to each operation in an analog-to-digital conversion; an interpolating comparator to compare the input analog signal and a determination voltage between first and second reference voltages corresponding to two comparators; a correction value acquisition circuit to calculate a correction value to correct an error between the input analog signal and the determination voltage; a correction value application circuit to set the correction value in the interpolating comparator; a test voltage generation circuit to supply the two comparators with a first test voltage corresponding to one of the determination voltages; a common voltage generation circuit to supply the two comparators with a second test voltage; and a correction value calculation circuit to calculate respective correction values corresponding to the determination voltages based on errors corresponding to the first
    Type: Application
    Filed: June 13, 2011
    Publication date: December 22, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Takumi DANJO
  • Publication number: 20110234440
    Abstract: An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.
    Type: Application
    Filed: March 24, 2011
    Publication date: September 29, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Takumi DANJO
  • Publication number: 20100245149
    Abstract: A comparison circuit comprising: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.
    Type: Application
    Filed: March 24, 2010
    Publication date: September 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Takumi DANJO, Takeshi Takayama, Sanroku Tsukamoto