Abstract: A folded cascode amplifier circuit includes: an input stage having a pair of transistors and configured to output a positive phase intermediate signal and an opposite phase intermediate signal; a cascode amplification stage having pairs of transistors connected in multiple stages, to which the positive phase intermediate signal and the opposite phase intermediate signal are supplied, and which is configured to output a positive phase output signal and an opposite phase output signal, which are differential signals; a first capacitor connected between a signal line of the positive phase intermediate signal and a signal line of the opposite phase output signal; and a second capacitor connected between a signal line of the opposite phase intermediate signal and a signal line of the positive phase output signal.

Abstract: An electronic circuit includes: a pair of first transistors in which a first control signal is inputted to at least one of a first control terminal; a comparator circuit that sets electric potentials of a pair of differential output terminals based on an electric current flowing through the pair of first transistors; second transistors that are coupled in series in a path between an electric power source and a node from at least one of the pair of differential output terminals and between the corresponding pair of first transistors, and having a second control terminals to which a second control signal is inputted; first switches that are respectively coupled in series to the second transistors in the path and that are turned ON in synchronization with a clock signal; and a generation circuit that generates the second control signal based on the clock signal.

Abstract: A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value.

Abstract: A folded cascode amplifier circuit includes: an input stage having a pair of transistors and configured to output a positive phase intermediate signal and an opposite phase intermediate signal; a cascode amplification stage having pairs of transistors connected in multiple stages, to which the positive phase intermediate signal and the opposite phase intermediate signal are supplied, and which is configured to output a positive phase output signal and an opposite phase output signal, which are differential signals; a first capacitor connected between a signal line of the positive phase intermediate signal and a signal line of the opposite phase output signal; and a second capacitor connected between a signal line of the opposite phase intermediate signal and a signal line of the positive phase output signal.

Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.

Abstract: A comparator includes: a differential amplifier circuit to operate based on a clock signal and output a first intermediate output and a second intermediate output corresponding to a first input signal and a second input signal respectively; and a differential latch circuit to operate based on the clock signal and vary a state based on the first intermediate output and the second intermediate output, the differential latch circuit having a controllable sensitivity with respect to a state variation of the first intermediate output and the second intermediate output.

Abstract: A comparator has a comparator circuit to output an output voltage based on a voltage difference between a first and second input voltage, a variable capacitor connected to an output terminal, an input voltage control circuit to generate a common voltage and add the common voltage to the first and the second input voltages, and a correction circuit to control the variable capacitor to control the common voltage. The correction circuit controls a first capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a first voltage difference, and controls a second capacitance value of the variable capacitor so that the output voltage is reversed when the voltage difference equals a second voltage value, and controls the common voltage so that a difference between the first capacitance value and the second capacitance value becomes equal to a predetermined capacitance value.

Abstract: A comparator includes: a differential amplifier of which operational state is switched in response to a clock-signal, and which outputs a first intermediate-output corresponding to a first input-signal and a second intermediate-output corresponding to a second input-signal; a differential latch circuit of which operational state is switched in response to the clock-signal, and a state of which is changed depending on the first intermediate-output and the second intermediate-output; a first adjuster configured to adjust a threshold of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output; and a second adjuster configured to adjust a threshold variation of the differential latch circuit with respect to a change of a state of the first intermediate-output and a change of a state of the second intermediate-output.

Abstract: Various embodiments of an analog-to-digital (A/D) device are described herein, with the A/D device using at least a comparison unit, a comparative operation control circuit, a delay circuit, and a successive operation control circuit arranged so as, it may, among other things, mitigate conversion errors that may be due to differences in properties of circuit elements therein. And the A/D device may be implemented in, among other things, a signal processing device.

Abstract: An analog-to-digital conversion circuit includes: comparators to compare an input analog signal and one of reference voltages corresponding to each operation in an analog-to-digital conversion; an interpolating comparator to compare the input analog signal and a determination voltage between first and second reference voltages corresponding to two comparators; a correction value acquisition circuit to calculate a correction value to correct an error between the input analog signal and the determination voltage; a correction value application circuit to set the correction value in the interpolating comparator; a test voltage generation circuit to supply the two comparators with a first test voltage corresponding to one of the determination voltages; a common voltage generation circuit to supply the two comparators with a second test voltage; and a correction value calculation circuit to calculate respective correction values corresponding to the determination voltages based on errors corresponding to the first

Abstract: An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.

Abstract: A comparison circuit includes: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.

Abstract: A comparison circuit includes: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.

Abstract: An analog-to-digital conversion circuit includes: comparators to compare an input analog signal and one of reference voltages corresponding to each operation in an analog-to-digital conversion; an interpolating comparator to compare the input analog signal and a determination voltage between first and second reference voltages corresponding to two comparators; a correction value acquisition circuit to calculate a correction value to correct an error between the input analog signal and the determination voltage; a correction value application circuit to set the correction value in the interpolating comparator; a test voltage generation circuit to supply the two comparators with a first test voltage corresponding to one of the determination voltages; a common voltage generation circuit to supply the two comparators with a second test voltage; and a correction value calculation circuit to calculate respective correction values corresponding to the determination voltages based on errors corresponding to the first

Abstract: An amplifying circuit includes a pair of MOS transistors; an amplifier that amplify a difference between potentials of differential output nodes coupled to drains of the pair of MOS transistors; cancel circuits that cause cancel current to flow to one of the differential output nodes when the amplifier amplifies a voltage between the differential output nodes and that shut off, after the amplifier performs the amplification operation, inflow of the cancel current; and a controller that performs setting so that a potential of first one of the differential input signals is equal to a potential of another one of the differential input signals, that compares, before the inflow of the cancel current, potentials generated at differential output nodes when the difference between potentials of the differential output nodes is amplified, and that sets the cancel current so that the potentials are reversed after the inflow of the cancel current.

Abstract: A comparison circuit comprising: an input circuit includes a first transistor for receiving a first signal, and a second transistor for receiving a second signal; a first current route of which the electric current is controlled by the first transistor; a second current route of which the electric current is controlled by the second transistor; a latch for amplifying potential difference between the first current route and the second current route; a comparative operation control circuit including a first switch for executing or blocking supply voltage to the drain of the first transistor, a second switch for executing or blocking supply voltage to the drain of the second transistor, and a third switch for executing supply voltage to the first current route and the second current route; a comparative operation setting circuit for controlling supply or blocking of supply of the first switch, the second switch, and the third switch.