Patents by Inventor Takumi Fujimoto
Takumi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955600Abstract: A solid-state battery is provided that allows the exterior can to be sufficiently crimped onto the seal can without leading to improper crimping, thus preventing entry of water from the outside. The solid-state battery 1 includes an exterior can 2, a seal can 3, facing the exterior can 2 and a power generation element 4 contained in the space between the exterior can 2 and seal can 3. The seal can 3 includes a flat portion 31 and a peripheral wall 32 that are contiguous to each other with a curved-surface portion 33 provided therebetween. A first clearance g1 is defined between the upper edge of the outer peripheral surface of the power generation element 4 and the border 10 between the inner surface of the flat portion 31 and the inner surface of the curved-surface portion 33, the first clearance having a radial dimension not larger than 2.0 mm at a position where its dimension is at its largest.Type: GrantFiled: August 31, 2020Date of Patent: April 9, 2024Assignee: Maxell, Ltd.Inventors: Yusuke Kawabata, Akihiro Fujimoto, Takumi Otsuka
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Publication number: 20230307066Abstract: A voltage generation circuit includes a plurality of charge pumps connected to a first node, and a control circuit that controls the number of active charge pumps among the plurality of charge pumps based on a period in which a voltage of the first node satisfies a condition.Type: ApplicationFiled: September 1, 2022Publication date: September 28, 2023Applicant: Kioxia CorporationInventor: Takumi FUJIMOTO
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Patent number: 11763890Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.Type: GrantFiled: August 23, 2021Date of Patent: September 19, 2023Assignee: Kioxia CorporationInventors: Yuki Shimizu, Yoshihiko Kamata, Tsukasa Kobayashi, Hideyuki Kataoka, Koji Kato, Takumi Fujimoto, Yoshinao Suzuki, Yuui Shimizu
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Patent number: 11742392Abstract: A silicon carbide semiconductor device, including a semiconductor substrate, a first semiconductor layer provided on a first surface of the semiconductor substrate, a second semiconductor layer provided on a first surface of the first semiconductor layer, a third semiconductor layer provided on a first surface of the second semiconductor layer, a fourth semiconductor layer provided on a first surface of the third semiconductor layer, a plurality of first semiconductor regions of selectively provided in the fourth semiconductor layer at a first surface thereof, a gate electrode provided via a gate insulating film in the fourth semiconductor layer, between the first semiconductor regions and the third semiconductor layer, a first electrode provided on the first surface of the fourth semiconductor layer and surfaces of the first semiconductor regions, and a second electrode provided on a second surface of the semiconductor substrate.Type: GrantFiled: June 25, 2021Date of Patent: August 29, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventors: Shingo Hayashi, Takumi Fujimoto
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Publication number: 20230223443Abstract: A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.Type: ApplicationFiled: March 13, 2023Publication date: July 13, 2023Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takumi FUJIMOTO
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Patent number: 11637182Abstract: A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.Type: GrantFiled: May 4, 2021Date of Patent: April 25, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takumi Fujimoto
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Patent number: 11386935Abstract: A charge pump circuit includes a first transistor having a drain connected to an input node, and a source connected to a first node; a second transistor having a drain connected to the first node, and a source connected to an output node; a first capacitor between the first and second nodes; a first inverter including an input node to which a clock signal is supplied and an output node connected to the second node via a first line; a first voltage detection circuit which includes an input node connected to the first line; a third transistor having a source connected to a third node, and a drain connected to the second node; a second inverter including an input node connected to the first voltage detection circuit and an output node connected to a fourth node via a second line; and a second capacitor between the third and fourth nodes.Type: GrantFiled: February 3, 2021Date of Patent: July 12, 2022Assignee: KIOXIA CORPORATIONInventor: Takumi Fujimoto
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Publication number: 20220069087Abstract: A silicon carbide semiconductor device, including a semiconductor substrate, a first semiconductor layer provided on a first surface of the semiconductor substrate, a second semiconductor layer provided on a first surface of the first semiconductor layer, a third semiconductor layer provided on a first surface of the second semiconductor layer, a fourth semiconductor layer provided on a first surface of the third semiconductor layer, a plurality of first semiconductor regions of selectively provided in the fourth semiconductor layer at a first surface thereof, a gate electrode provided via a gate insulating film in the fourth semiconductor layer, between the first semiconductor regions and the third semiconductor layer, a first electrode provided on the first surface of the fourth semiconductor layer and surfaces of the first semiconductor regions, and a second electrode provided on a second surface of the semiconductor substrate.Type: ApplicationFiled: June 25, 2021Publication date: March 3, 2022Applicant: FUJI ELECTRIC CO., LTD.Inventors: Shingo HAYASHI, Takumi FUJIMOTO
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Patent number: 11251271Abstract: A semiconductor device having a semiconductor substrate that includes first to third epitaxial layers provided sequentially on a starting substrate, the third epitaxial layer forming a pn junction with the second epitaxial layer, and including a plurality of first semiconductor regions formed on a second semiconductor region. The semiconductor device further includes a plurality of trenches penetrating the first and second semiconductor regions to reach the second epitaxial layer, a plurality of gate electrodes provided in the trenches respectively via a gate insulating film, a metal film in ohmic contact with the first semiconductor regions, a first electrode electrically connected to the first semiconductor regions via the metal film, and a second electrode provided at a back surface of the starting substrate. Each of the starting substrate and the first to third epitaxial layers contains silicon carbide.Type: GrantFiled: September 30, 2020Date of Patent: February 15, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takumi Fujimoto
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Publication number: 20210383868Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Inventors: Yuki SHIMIZU, Yoshihiko KAMATA, Tsukasa KOBAYASHI, Hideyuki KATAOKA, Koji KATO, Takumi FUJIMOTO, Yoshinao SUZUKI, Yuui SHIMIZU
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Patent number: 11133066Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.Type: GrantFiled: July 21, 2020Date of Patent: September 28, 2021Assignee: KIOXIA CORPORATIONInventors: Yuki Shimizu, Yoshihiko Kamata, Tsukasa Kobayashi, Hideyuki Kataoka, Koji Kato, Takumi Fujimoto, Yoshinao Suzuki, Yuui Shimizu
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Publication number: 20210287722Abstract: A charge pump circuit includes a first transistor having a drain connected to an input node, and a source connected to a first node; a second transistor having a drain connected to the first node, and a source connected to an output node; a first capacitor between the first and second nodes; a first inverter including an input node to which a clock signal is supplied and an output node connected to the second node via a first line; a first voltage detection circuit which includes an input node connected to the first line; a third transistor having a source connected to a third node, and a drain connected to the second node; a second inverter including an input node connected to the first voltage detection circuit and an output node connected to a fourth node via a second line; and a second capacitor between the third and fourth nodes.Type: ApplicationFiled: February 3, 2021Publication date: September 16, 2021Inventor: Takumi FUJIMOTO
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Publication number: 20210257455Abstract: A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.Type: ApplicationFiled: May 4, 2021Publication date: August 19, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takumi FUJIMOTO
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Patent number: 11038020Abstract: A silicon carbide semiconductor device includes a semiconductor substrate and a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a gate electrode provided opposing at least a surface of the second semiconductor layer between the first semiconductor region and the first semiconductor layer, across a gate insulating film; and a first electrode provided on surfaces of the first semiconductor region and the second semiconductor layer. Protons are implanted in a first region of the semiconductor substrate, spanning at least 2 ?m from a surface of the semiconductor substrate facing toward the first semiconductor layer; and in a second region of the first semiconductor layer, spanning at least 3 ?m from a surface of the first semiconductor layer facing toward the semiconductor substrate. The protons having a concentration in a range from 1×1013/cm3 to 1×1015/cm3.Type: GrantFiled: September 24, 2018Date of Patent: June 15, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takumi Fujimoto
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Publication number: 20210167173Abstract: A semiconductor device having a semiconductor substrate that includes first to third epitaxial layers provided sequentially on a starting substrate, the third epitaxial layer forming a pn junction with the second epitaxial layer, and including a plurality of first semiconductor regions formed on a second semiconductor region. The semiconductor device further includes a plurality of trenches penetrating the first and second semiconductor regions to reach the second epitaxial layer, a plurality of gate electrodes provided in the trenches respectively via a gate insulating film, a metal film in ohmic contact with the first semiconductor regions, a first electrode electrically connected to the first semiconductor regions via the metal film, and a second electrode provided at a back surface of the starting substrate. Each of the starting substrate and the first to third epitaxial layers contains silicon carbide.Type: ApplicationFiled: September 30, 2020Publication date: June 3, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takumi FUJIMOTO
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Patent number: 10896960Abstract: An inverter circuit is connected serially with a first silicon carbide MOSFET and a second silicon carbide MOSFET. During a dead time when the first silicon carbide MOSFET and the second silicon carbide MOSFET are OFF, transient current of at least 100 A/cm2 flows in a built-in diode of the first silicon carbide MOSFET and a built-in diode of the second silicon carbide MOSFET.Type: GrantFiled: October 24, 2018Date of Patent: January 19, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Takumi Fujimoto
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Publication number: 20200350016Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.Type: ApplicationFiled: July 21, 2020Publication date: November 5, 2020Inventors: Yuki SHIMIZU, Yoshihiko KAMATA, Tsukasa KOBAYASHI, Hideyuki KATAOKA, Koji KATO, Takumi FUJIMOTO, Yoshinao SUZUKI, Yuui SHIMIZU
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Patent number: 10762963Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.Type: GrantFiled: September 2, 2018Date of Patent: September 1, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuki Shimizu, Yoshihiko Kamata, Tsukasa Kobayashi, Hideyuki Kataoka, Koji Kato, Takumi Fujimoto, Yoshinao Suzuki, Yuui Shimizu
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Publication number: 20190348120Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.Type: ApplicationFiled: September 2, 2018Publication date: November 14, 2019Inventors: Yuki SHIMIZU, Yoshihiko KAMATA, Tsukasa KOBAYASHI, Hideyuki KATAOKA, Koji KATO, Takumi FUJIMOTO, Yoshinao SUZUKI, Yuui SHIMIZU
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Patent number: 10340817Abstract: The inverter circuit has a first silicon carbide MOSFET and a second silicon carbide MOSFET connected in series and external freewheel diodes respectively connected in anti-parallel to the first and second MOSFETs. The inverter circuit is configured such that during a deadtime when the first silicon carbide MOSFET and the second silicon carbide MOSFET are OFF and freewheeling current starts flowing, a pulse width of a transient current flowing to a built-in diode of the first silicon carbide MOSFET or a built-in diode of the second silicon carbide MOSFET is less than 2 ?s.Type: GrantFiled: September 7, 2018Date of Patent: July 2, 2019Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takumi Fujimoto, Mikiya Chounabayashi