Patents by Inventor Takumi Fujimoto
Takumi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190198620Abstract: An inverter circuit is connected serially with a first silicon carbide MOSFET and a second silicon carbide MOSFET. During a dead time when the first silicon carbide MOSFET and the second silicon carbide MOSFET are OFF, transient current of at least 100 A/cm2 flows in a built-in diode of the first silicon carbide MOSFET and a built-in diode of the second silicon carbide MOSFET.Type: ApplicationFiled: October 24, 2018Publication date: June 27, 2019Applicant: FUJI ELECTRIC CO., LTD.Inventor: Takumi FUJIMOTO
-
Publication number: 20190165102Abstract: A silicon carbide semiconductor device includes a semiconductor substrate and a first semiconductor layer of the first conductivity type; a second semiconductor layer of a second conductivity type; a first semiconductor region of the first conductivity type; a gate electrode provided opposing at least a surface of the second semiconductor layer between the first semiconductor region and the first semiconductor layer, across a gate insulating film; and a first electrode provided on surfaces of the first semiconductor region and the second semiconductor layer. Protons are implanted in a first region of the semiconductor substrate, spanning at least 2 ?m from a surface of the semiconductor substrate facing toward the first semiconductor layer; and in a second region of the first semiconductor layer, spanning at least 3 ?m from a surface of the first semiconductor layer facing toward the semiconductor substrate. The protons having a concentration in a range from 1×1013/cm3 to 1×1015/cm3.Type: ApplicationFiled: September 24, 2018Publication date: May 30, 2019Applicant: Fuji Electric Co., Ltd.Inventor: Takumi FUJIMOTO
-
Publication number: 20190115850Abstract: The inverter circuit has a first silicon carbide MOSFET and a second silicon carbide MOSFET connected in series and external freewheel diodes respectively connected in anti-parallel to the first and second MOSFETs. The inverter circuit is configured such that during a deadtime when the first silicon carbide MOSFET and the second silicon carbide MOSFET are OFF and freewheeling current starts flowing, a pulse width of a transient current flowing to a built-in diode of the first silicon carbide MOSFET or a built-in diode of the second silicon carbide MOSFET is less than 2 ?s.Type: ApplicationFiled: September 7, 2018Publication date: April 18, 2019Applicant: Fuji Electric Co., Ltd.Inventors: Takumi FUJIMOTO, Mikiya Chounabayashi
-
Patent number: 10147797Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure, an interlayer insulating film formed on the insulated gate structure, a poly-silicon film formed on the interlayer insulating film, and a main electrode formed on the poly-silicon film and in electrical connection with the silicon carbide semiconductor structure. The insulated gate structure includes a gate insulating film, which is a silicon dioxide film contacting the silicon carbide semiconductor structure, and a gate electrode formed on the gate insulating film.Type: GrantFiled: May 1, 2017Date of Patent: December 4, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takumi Fujimoto, Naoki Kumagai
-
Patent number: 10096680Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.Type: GrantFiled: March 24, 2017Date of Patent: October 9, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Naoki Kumagai, Takashi Tsutsumi, Yoshiyuki Sakai, Yasuhiko Oonishi, Takumi Fujimoto, Kenji Fukuda, Shinsuke Harada, Mitsuo Okamoto
-
Patent number: 9893162Abstract: Heat treatment is performed twice with respect to a silicon carbide substrate. In the first heat treatment process, after Si ions are implanted in a front surface of the silicon carbide substrate, the silicon carbide substrate contacting an electrode film is heat treated, and a precursor layer of a thermal reaction layer is formed between the electrode film and the silicon carbide substrate that includes a high-concentration impurity region. Thereafter, the unreacted electrode film remaining on the precursor layer of the thermal reaction layer and on an oxide film is removed. In the subsequent second heat treatment process, the silicon carbide substrate from which the unreacted electrode film has been removed is heat treated and the precursor layer of the thermal reaction layer at a bottom area of the opening is converted into the thermal reaction layer.Type: GrantFiled: February 21, 2017Date of Patent: February 13, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Naoyuki Ohse, Takumi Fujimoto, Yoshiyuki Sakai
-
Publication number: 20170271472Abstract: Heat treatment is performed twice with respect to a silicon carbide substrate. In the first heat treatment process, after Si ions are implanted in a front surface of the silicon carbide substrate, the silicon carbide substrate contacting an electrode film is heat treated, and a precursor layer of a thermal reaction layer is formed between the electrode film and the silicon carbide substrate that includes a high-concentration impurity region. Thereafter, the unreacted electrode film remaining on the precursor layer of the thermal reaction layer and on an oxide film is removed. In the subsequent second heat treatment process, the silicon carbide substrate from which the unreacted electrode film has been removed is heat treated and the precursor layer of the thermal reaction layer at a bottom area of the opening is converted into the thermal reaction layer.Type: ApplicationFiled: February 21, 2017Publication date: September 21, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Naoyuki OHSE, Takumi FUJIMOTO, Yoshiyuki SAKAI
-
Publication number: 20170236914Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure, an interlayer insulating film formed on the insulated gate structure, a poly-silicon film formed on the interlayer insulating film, and a main electrode formed on the poly-silicon film and in electrical connection with the silicon carbide semiconductor structure. The insulated gate structure includes a gate insulating film, which is a silicon dioxide film contacting the silicon carbide semiconductor structure, and a gate electrode formed on the gate insulating film.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takumi FUJIMOTO, Naoki KUMAGAI
-
Publication number: 20170194438Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure including a gate insulating film contacting the silicon carbide semiconductor structure and a gate electrode formed on the gate insulating film, an interlayer insulating film covering the insulated gate structure, a metal layer provided on the interlayer insulating film for absorbing or blocking hydrogen, and a main electrode provided on the metal layer and electrically connected to the silicon carbide semiconductor structure.Type: ApplicationFiled: March 24, 2017Publication date: July 6, 2017Applicant: FUJI ELECTRIC CO., LTD.Inventors: Naoki KUMAGAI, Takashi TSUTSUMI, Yoshiyuki SAKAI, Yasuhiko OONISHI, Takumi FUJIMOTO, Kenji FUKUDA, Shinsuke HARADA, Mitsuo OKAMOTO
-
Patent number: 9496370Abstract: A screen oxide film is formed on an n? drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n? drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p? well regions (10) are formed.Type: GrantFiled: March 11, 2016Date of Patent: November 15, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasushi Niimura, Sota Watanabe, Hidenori Takahashi, Takumi Fujimoto, Takeyoshi Nishimura, Takamasa Wakabayashi
-
Publication number: 20160197163Abstract: A screen oxide film is formed on an n? drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n? drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p? well regions (10) are formed.Type: ApplicationFiled: March 11, 2016Publication date: July 7, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasushi NIIMURA, Sota WATANABE, Hidenori TAKAHASHI, Takumi FUJIMOTO, Takeyoshi NISHIMURA, Takamasa WAKABAYASHI
-
Patent number: 9312379Abstract: A screen oxide film is formed on an n-drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n-drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p- well regions (10) are formed.Type: GrantFiled: July 28, 2015Date of Patent: April 12, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasushi Niimura, Sota Watanabe, Hidenori Takahashi, Takumi Fujimoto, Takeyoshi Nishimura, Takamasa Wakabayashi
-
Publication number: 20160005856Abstract: A screen oxide film is formed on an n-drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n-drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p- well regions (10) are formed.Type: ApplicationFiled: July 28, 2015Publication date: January 7, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasushi NIIMURA, Sota WATANABE, Hidenori TAKAHASHI, Takumi FUJIMOTO, Takeyoshi NISHIMURA, Takamasa WAKABAYASHI
-
Patent number: 9136352Abstract: A screen oxide film is formed on an n? drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n-drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p? well regions (10) are formed.Type: GrantFiled: July 29, 2010Date of Patent: September 15, 2015Assignee: FUJI ELECTRIC CO., LTD.Inventors: Yasushi Niimura, Sota Watanabe, Hidenori Takahashi, Takumi Fujimoto, Takeyoshi Nishimura, Takamasa Wakabayashi
-
Publication number: 20120139036Abstract: A screen oxide film is formed on an n? drift layer (2) that is disposed on an anterior side of an n-type low-resistance layer (1), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film (61) is formed. N-type impurity ions at a concentration higher than that of the n? drift layer are implanted through the nitride shielding film (61) from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer (7) is formed. The screen oxide film is removed. A gate oxide film (3a) is formed. A gate electrode (9) is formed on the gate oxide film (3a). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode (9) and the nitride shielding film (61) as a mask and thereby, p? well regions (10) are formed.Type: ApplicationFiled: July 29, 2010Publication date: June 7, 2012Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yasushi Niimura, Sota Watanabe, Hidenori Takahashi, Takumi Fujimoto, Takeyoshi Nishimura, Takamasa Wakabayashi