Abstract: An aluminum alloy for automobile wheels which contains Si in a range of 8.0% to 11.5% by mass, Cu in a range of 0.7% to 1.2% by mass, Mg in a range of 0.2% to 0.6% by mass, Mn in a range of 0.30% to 0.60% by mass, Fe in a range of 0.10% to 0.30% by mass, Cr in a range of 0.01% to 0.03% by mass, and balance Al with inevitable impurities. The aluminum alloy does not contain, per 1182 ?m2, two or more crystallized products containing 1% by mass or more of Cu and having a circle equivalent diameter exceeding 5 ?m, does not contain, per 1182 ?m2, two or more Cr-containing intermetallic compounds having a length of 8 ?m or more, and does not contain, per 4726 ?m2, two or more primary crystal Si particles having a circle equivalent diameter exceeding 10 ?m.

Abstract: An aluminum alloy for a sliding component containing 8.0% to 12.0% by mass of Si, 0.8% to 1.1% by mass of Cu, 0.4% to 0.6% by mass of Mg, 0.30% to 0.60% by mass of Mn, 0.01% to 0.03% by mass of Cr, 0.10% to 0.30% by mass of Fe, 0.0005% to 0.0050% by mass of Ca, 0.00005% to 0.03000% by mass of Sr, and balance Al with inevitable impurities, in which a ratio Sr/Ca of a Sr content to a Ca content is in a range of 0.01 to 30, a tensile strength at 25° C. is within a range of 330 MPa to 380 MPa, the aluminum alloy does not contain, per 1182 ?m2, two or more crystallized products containing 1% by mass or more of Cu and having a circle equivalent diameter exceeding 5 ?m, and the aluminum alloy does not contain, per 1182 ?m2, two or more Cr-containing intermetallic compounds having a length of 8 ?m or more.

Abstract: An aluminum alloy for sliding components contains 8.0-11.5% by mass of Si, 0.7-1.2% by mass of Cu, 0.2-0.6% by mass of Mg, 0.30-0.60% by mass of Mn, 0.10-0.30% by mass of Fe, 0.01-0.03% by mass of Cr, and balance Al with inevitable impurities, in which a tensile strength at 25° C. is within a range of 330 MPa or more and 380 MPa or less, the aluminum alloy does not contain, per 1182 ?m2, two or more crystallized products containing 1% by mass or more of Cu and having a circle equivalent diameter exceeding 5 ?m, and the aluminum alloy does not contain, per 1182 ?m2, two or more Cr-containing intermetallic compounds having a length of 8 ?m or more, and does not contain, per 4726 ?m2, two or more primary crystal Si particles having a circle equivalent diameter exceeding 10 ?m.

Abstract: Provided is a production method of an aluminum alloy forging for an automobile suspension having a disturbance affectable surface with not excessively notch-sensitive. The production method includes, as heat treatment processes, a solution heat treatment process, a quenching process, and an artificial age hardening process. The quenching process is performed by bringing a lower surface of the aluminum forging to be disposed on a ground side when assembled to the automobile into contact with water before an upper surface of the aluminum forging opposite to the lower surface is brought into contact with the water.

Abstract: Provided is a production method of an aluminum alloy forging for an automobile suspension having a disturbance affectable surface with not excessively notch-sensitive. The production method includes, as heat treatment processes, a solution heat treatment process, a quenching process, and an artificial age hardening process. The quenching process is performed by bringing a lower surface of the aluminum forging to be disposed on a ground side when assembled to the automobile into contact with water after an upper surface of the aluminum forging opposite to the lower surface is brought into contact with the water.

Abstract: Provided is an aluminum alloy material with high strength and low thermal expansion coefficient even under high temperature environments. An aluminum alloy material according to the present invention has a composition consisting of: Si: 13 mass % to 15 mass %, Cu: 2.0 mass % to 6.0 mass %, Mg: 0.2 mass % to 1.5 mass %, Fe: 0.4 mass % to 0.8 mass %, Ni: 0.2 mass % to 0.8 mass %, P: 0.005 mass % to 0.015 mass %, and the balance being Al and inevitable impurities.

Abstract: A processor includes: an address generating unit that, when an instruction decoded by a decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets; a plurality of instruction queues that hold the generated address sets corresponding to the respective operand sets, in correspondence to respective processing units; and a plurality of processing units that perform the arithmetic processing in parallel on the operand sets obtained based on the respective address sets outputted by the plurality of instruction queues.

Abstract: Provided is a method of producing an Al alloy cast material capable of properly adjusting an additive amount of Ti. The present invention is directed to a method of producing an Al alloy cast material in which an Al alloy molten metal supplied to a casting machine through a molten metal passage is solidified by the casting machine to produce an Al alloy cast material. The production method of the present invention includes a primary Ti-addition step of preliminarily adding Ti to an Al alloy molten metal before flowing through a molten metal passage and a secondary Ti-addition step of adding Ti to an Al alloy molten metal flowing through a molten metal passage by a feeder.

Abstract: A plurality of floating-point registers store data therein. A processing execution unit executes arithmetic processing by using data stored in the floating-point registers. A first switch and a second switch select a route connecting the processing execution unit and the floating-point registers. A switch control unit controls the first switch and the second switch so as to switch a route to be selected, based on a switching instruction from the processing execution unit.

Abstract: Provided is an aluminum alloy material with high strength and low thermal expansion coefficient even under high temperature environments. An aluminum alloy material according to the present invention has a composition consisting of: Si: 13 mass % to 15 mass %, Cu: 2.0 mass % to 6.0 mass %, Mg: 0.2 mass % to 1.5 mass %, Fe: 0.4 mass % to 0.8 mass %, Ni: 0.2 mass % to 0.8 mass %, P: 0.005 mass % to 0.015 mass %, and the balance being Al and inevitable impurities.

Abstract: A plurality of floating-point registers store data therein. A processing execution unit executes arithmetic processing by using data stored in the floating-point registers. A first switch and a second switch select a route connecting the processing execution unit and the floating-point registers. A switch control unit controls the first switch and the second switch so as to switch a route to be selected, based on a switching instruction from the processing execution unit.

Abstract: A processor includes: an address generating unit that, when an instruction decoded by a decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets; a plurality of instruction queues that hold the generated address sets corresponding to the respective operand sets, in correspondence to respective processing units; and a plurality of processing units that perform the arithmetic processing in parallel on the operand sets obtained based on the respective address sets outputted by the plurality of instruction queues.

Abstract: A processor includes: a storage unit that stores instructions; a counting unit that specifies an instruction to be decoded by a count value; a decoding unit that decodes an instruction; and a control unit that, when the decoded instruction is a repeat instruction, updates the count value of the counting unit so as to cause repeat target instructions in number corresponding to a designated number of instructions, out of instructions succeeding the repeat instruction, to be repeatedly executed a designated number of repetition times, and generates updated operands being operation objects of the repeat target instructions that are to be executed for the second or later time, and when the repeat target instructions are to be executed for the second or later time, updates operands of the repeat target instructions for use in the second or later time execution, to the generated updated operands and outputs the updated operands.

Abstract: A data compression apparatus includes a memory and a processor. The processor extracts a second character string as a matching string from a character string after a first character string in a character string of data before compression that is stored in the memory, the second character string being identical with the first character string, and identifies a length of the matching string, and a relative position indicating how many addresses the first character string precedes the second character string by. The processor extracts a third character string having a length that is less than the relative position from the extracted second character string. The processor encodes a length of the third character string. The processor encodes the relative position.

Abstract: A data compression apparatus includes a memory and a processor. The processor extracts a second character string as a matching string from a character string after a first character string in a character string of data before compression that is stored in the memory, the second character string being identical with the first character string, and identifies a length of the matching string, and a relative position indicating how many addresses the first character string precedes the second character string by. The processor extracts a third character string having a length that is less than the relative position from the extracted second character string. The processor encodes a length of the third character string. The processor encodes the relative position.

Abstract: In a data compression apparatus, a search unit examines the sequence of symbols in compression target data, and searches for a second symbol string having the same sequence of symbols as a first symbol string that occurred previously, and a code generation unit encodes the second symbol string into a code containing information that specifies a block to which the beginning of the first symbol string belongs. In a data decompression apparatus, a code acquisition unit sequentially acquires codes from the beginning of the compressed data, and when the code of the second symbol string is acquired, a decompression unit acquires, from a storage device, one or more blocks starting with a block to which the beginning of the decompressed first symbol string belongs, on the basis of the information contained in the acquired code, and decompresses the second symbol string.

Abstract: A packet multiplexing control method and equipment using the method are realized by a simple control method with reduced hardware, enabling to provide low cost, efficient and fair bandwidth control corresponding to traffic characteristic of users. The packet multiplexing control method includes the steps of extracting a header part in each packet data received from a plurality of terminals; learning an address in the extracted header part; and controlling either admission processing or discard processing of the received packet according to the result of learning the address.

Abstract: A computer-implemented method and system for performing an arithmetic shift right by n of an m-bit negative number. A right shifter executes a logical shift right operation on the number to be shifted. A left shifter performs a left shift on an m-bit mask of ones, left shifting the mask by the one's complement of n. An OR operation is then performed on the results of the two shifting operations, producing the desired arithmetic shift right result.

Abstract: A packet multiplexing control method and equipment using the method are realized by a simple control method with reduced hardware, enabling to provide low cost, efficient and fair bandwidth control corresponding to traffic characteristic of users. The packet multiplexing control method includes the steps of extracting a header part in each packet data received from a plurality of terminals; learning an address in the extracted header part; and controlling either admission processing or discard processing of the received packet according to the result of learning the address.

Abstract: An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution.An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions.