Abstract: Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size.

Abstract: A main controller of a recording medium dualization system reads, when the power is turned on, three types of information: USE information (status information of a recording medium of each medium board) indicating whether or not the medium can be used; ACT information indicating which of the recording mediums is or was used in an active system; and PWON information indicating whether or not the power for the recording medium is turned on, whereupon the main controller sets the information to denote that the master system is an active system and executes a mirroring process whereby the USE information and the PWON information of the slave system are identical to the master system. When it is found that the recording medium of the master system is removed, on the basis of the USE and ACT information, the slave system is switched to an active system, and the corresponding information setting is performed.

Abstract: A multi-CPU system including a fault monitoring facility comprises a plurality of central processing units interconnected through a system bus and sending and receiving data through a plurality of bus interface units inserted in the system bus. A fault monitoring bus in parallel with the system bus is commonly accessed by the bus interface units. A bus interface unit which detects a fault notifies the other bus interface units simultaneously using the fault monitoring bus. Data-originating interface units and data-destination interface units receive fault information of the location and type of fault, which has occurred. Swift recovery from a faulty state is enabled.

Abstract: An apparatus for controlling synchronization in a system having at least first and second units each having internal circuits includes signal paths through which a control signal output from a second unit is sent to a first unit and a control signal output from the first unit is sent to the second unit. A first preparatory process part carries out a process to place the internal circuits of the second unit in an operating state when the second unit is connected to the system and for outputting a control signal to the signal paths. A first function mask control part is provided for stopping the operation of the internal circuits of the second unit when a control signal from the first unit is not received by the second unit, and for restarting the operation of the internal circuits when the control signal is received.

Abstract: A firmware trace data acquisition method is constituted such that there are provided a monitoring part for monitoring firmware processes and a DMA part for transferring data to a trace data storing part in accordance with an instruction from the monitoring part, such that labels are attached to the plurality of process modules stored in a firmware storing part, and such that each of the process modules activated notifies the monitoring part of the label attached to itself. The monitoring part latches the label that it is notified of and monitors the execution of the corresponding process such that, when an abnormality is detected during the execution, the monitoring part controls the DMA part so as to transfer detailed data, derived from the process module corresponding to the label latched, to the trace data storing part, and such that, when there is no abnormality detected, the monitoring part allows the DMA part to transfer the latched label to the trace data storing part.