Patents by Inventor Takumi Nakahata
Takumi Nakahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8841541Abstract: In a solar battery including: a photoelectric conversion layer that converts light into electricity; and a reflecting electrode layer that is provided on an opposite side of a light incident side in the photoelectric conversion layer and reflects light passed through the photoelectric conversion layer to the photoelectric conversion layer side, to realize a reflecting electrode layer having excellent adhesion and thermal corrosion resistance, stable electrical characteristics and satisfactory light reflection characteristics and to obtain a solar battery having high reliability, excellent electrical characteristics and optical characteristics, the reflecting electrode layer includes, on the photoelectric conversion layer side, a metal layer containing silver as a main component and containing nitrogen.Type: GrantFiled: September 4, 2009Date of Patent: September 23, 2014Assignee: Mitsubishi Electric CorporationInventors: Takumi Nakahata, Kazunori Inoue, Yusuke Yamagata
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A1 alloy film, electronic device, and active matrix substrate for use in electrooptic display device
Patent number: 8558248Abstract: In accordance with one aspect of the present invention, an Al alloy film contains a first additive element composed of Ni, and at least one type of second additive element selected from the group consisting of Group 2A alkaline earth metals and Groups 3B and 4B metalloids in Period 2 or 3 of the periodic table of the elements. Furthermore, the composition ratio of the first additive element is 0.5-5 at %, and the composition ratio of the second additive element is 0.1-3 at %.Type: GrantFiled: September 19, 2008Date of Patent: October 15, 2013Assignee: Mitsubishi Electric CorporationInventors: Kazunori Inoue, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura, Takumi Nakahata -
Patent number: 8405091Abstract: A display device includes a metal conductive layer formed on a substrate, a transparent electrode film formed on the substrate and joined to the metal conductive layer and an interlayer insulating film isolating the metal conductive layer and the transparent conductive film. The metal conductive layer has a lower aluminum layer made of aluminum or aluminum alloy, an intermediate impurity containing layer made of aluminum or aluminum alloy containing impurities and formed on a substantially entire upper surface of the lower aluminum layer and an upper aluminum layer made of aluminum or aluminum alloy and formed on the intermediate impurity containing layer. In the interlayer insulating film and the upper aluminum layer, a contact hole penetrates therethrough and locally exposes the intermediate impurity containing layer, and the transparent electrode film is joined to the metal conductive layer in the intermediate impurity containing layer exposed from the contact hole.Type: GrantFiled: February 4, 2008Date of Patent: March 26, 2013Assignee: Mitsubishi Electric CorporationInventors: Takumi Nakahata, Kazunori Inoue, Koji Oda, Naoki Nakagawa, Nobuaki Ishiga
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Publication number: 20120160319Abstract: In a solar battery including: a photoelectric conversion layer that converts light into electricity; and a reflecting electrode layer that is provided on an opposite side of a light incident side in the photoelectric conversion layer and reflects light passed through the photoelectric conversion layer to the photoelectric conversion layer side, to realize a reflecting electrode layer having excellent adhesion and thermal corrosion resistance, stable electrical characteristics and satisfactory light reflection characteristics and to obtain a solar battery having high reliability, excellent electrical characteristics and optical characteristics, the reflecting electrode layer includes, on the photoelectric conversion layer side, a metal layer containing silver as a main component and containing nitrogen.Type: ApplicationFiled: September 4, 2009Publication date: June 28, 2012Applicant: Mitsubishi Electric CorporationInventors: Takumi Nakahata, Kazunori Inoue, Yusuke Yamagata
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Patent number: 8040476Abstract: The display device includes a pair of insulating substrates arranged so as to be opposed, a bonding layer, and a strain suppressing plate. The bonding layer is provided on the outer surface side of one insulating substrate. The strain suppressing plate has rigidity higher than that of the insulating substrate to suppress the strain caused by curving the insulating substrate. The strain suppressing plate is fixed to the insulating substrate by the bonding layer.Type: GrantFiled: May 26, 2009Date of Patent: October 18, 2011Assignee: Mitsubishi Electric CorporationInventors: Takumi Nakahata, Takanori Okumura, Yusuke Yamagata, Naoki Nakagawa, Masafumi Agari, Tetsuya Satake, Toru Kokogawa, Kenji Arita
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Patent number: 7834962Abstract: In a liquid crystal display (10) having a curved display surface, long sides of pixel structures (11) are arranged along the curve direction (Y) of the display surface and on a side of counter substrate provided is a black matrix having a black matrix opening (41a) whose length in the curve direction (Y) is not longer than E?L {(T1/2)+(T2/2)+d}/R, assuming that the length of the display surface in the curve direction (Y) is L, the thickness of an array substrate is T1, the thickness of the counter substrate is T2, the size of the gap between the array substrate and the counter substrate is d, the radius of curvature of the curved display surface is R and the length of a long side of a pixel electrode (29) provided in each of the pixel structures (11) is E. It thereby becomes possible to suppress display unevenness resulting from positional misalignment of the two substrates due to curvature and provide a liquid crystal display achieving a high-quality display image.Type: GrantFiled: December 8, 2008Date of Patent: November 16, 2010Assignee: Mitsubishi Electric CorporationInventors: Tetsuya Satake, Takumi Nakahata, Takanori Okumura, Yusuke Yamagata, Takeshi Ono, Naoki Nakagawa, Suguru Nagae
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Patent number: 7825515Abstract: A semiconductor device includes a film containing silicon as the main ingredient, and an aluminum alloy film, such as a source electrode and a drain electrode, that is directly connected to the film containing silicon as the main ingredient, such as an ohmic low-resistance Si film, and contains at least Al, Ni, and N in the vicinity of the bonding interface. The Aluminum alloy film has a good contact characteristic when directly connected to the film containing silicon as the main ingredient without having a barrier layer formed of high melting point metal.Type: GrantFiled: September 8, 2008Date of Patent: November 2, 2010Assignee: Mitsubishi Electric CorporationInventors: Kazunori Inoue, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura, Takumi Nakahata, Kazumasa Kawase
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Publication number: 20100078816Abstract: A display device includes a metal conductive layer formed on a substrate, a transparent electrode film formed on the substrate and joined to the metal conductive layer and an interlayer insulating film isolating the metal conductive layer and the transparent conductive film. The metal conductive layer has a lower aluminum layer made of aluminum or aluminum alloy, an intermediate impurity containing layer made of aluminum or aluminum alloy containing impurities and formed on a substantially entire upper surface of the lower aluminum layer and an upper aluminum layer made of aluminum or aluminum alloy and formed on the intermediate impurity containing layer. In the interlayer insulating film and the upper aluminum layer, a contact hole penetrates therethrough and locally exposes the intermediate impurity containing layer, and the transparent electrode film is joined to the metal conductive layer in the intermediate impurity containing layer exposed from the contact hole.Type: ApplicationFiled: February 4, 2008Publication date: April 1, 2010Applicant: Mitsubishi Electric CorporationInventors: Takumi Nakahata, Kazunori Inoue, Koji Oda, Naoki Nakagawa, Nobuaki Ishiga
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Publication number: 20090290113Abstract: The display device includes a pair of insulating substrates arranged so as to be opposed, a bonding layer, and a strain suppressing plate. The bonding layer is provided on the outer surface side of one insulating substrate. The strain suppressing plate has rigidity higher than that of the insulating substrate to suppress the strain caused by curving the insulating substrate. The strain suppressing plate is fixed to the insulating substrate by the bonding layer.Type: ApplicationFiled: May 26, 2009Publication date: November 26, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takumi Nakahata, Takanori Okumura, Yusuke Yamagata, Naoki Nakagawa, Masafumi Agari, Tetsuya Satake, Toru Kokogawa, Kenji Arita
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Publication number: 20090161048Abstract: In a liquid crystal display (10) having a curved display surface, long sides of pixel structures (11) are arranged along the curve direction (Y) of the display surface and on a side of counter substrate provided is a black matrix having a black matrix opening (41a) whose length in the curve direction (Y) is not longer than E?L {(T1/2)+(T2/2)+d}/R, assuming that the length of the display surface in the curve direction (Y) is L, the thickness of an array substrate is T1, the thickness of the counter substrate is T2, the size of the gap between the array substrate and the counter substrate is d, the radius of curvature of the curved display surface is R and the length of a long side of a pixel electrode (29) provided in each of the pixel structures (11) is E. It thereby becomes possible to suppress display unevenness resulting from positional misalignment of the two substrates due to curvature and provide a liquid crystal display achieving a high-quality display image.Type: ApplicationFiled: December 8, 2008Publication date: June 25, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Tetsuya SATAKE, Takumi NAKAHATA, Takanori OKUMURA, Yusuke YAMAGATA, Takeshi ONO, Naoki NAKAGAWA, Suguru NAGAE
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A1 ALLOY FILM, ELECTRONIC DEVICE, AND ACTIVE MATRIX SUBSTRATE FOR USE IN ELECTROOPTIC DISPLAY DEVICE
Publication number: 20090134407Abstract: In accordance with one aspect of the present invention, an Al alloy film contains a first additive element composed of Ni, and at least one type of second additive element selected from the group consisting of Group 2A alkaline earth metals and Groups 3B and 4B metalloids in Period 2 or 3 of the periodic table of the elements. Furthermore, the composition ratio of the first additive element is 0.5-5 at %, and the composition ratio of the second additive element is 0.1-3 at %.Type: ApplicationFiled: September 19, 2008Publication date: May 28, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazunori INOUE, Nobuaki ISHIGA, Kensuke NAGAYAMA, Naoki TSUMURA, Takumi NAKAHATA -
Publication number: 20090065942Abstract: A semiconductor device includes a film containing silicon as the main ingredient, and an aluminum alloy film, such as a source electrode and a drain electrode, that is directly connected to the film containing silicon as the main ingredient, such as an ohmic low-resistance Si film, and contains at least Al, Ni, and N in the vicinity of the bonding interface. The Aluminum alloy film has a good contact characteristic when directly connected to the film containing silicon as the main ingredient without having a barrier layer formed of high melting point metal.Type: ApplicationFiled: September 8, 2008Publication date: March 12, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazunori INOUE, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura, Takumi Nakahata, Kazumasa Kawase
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Publication number: 20060273422Abstract: A thin film transistor for characteristic inspection has a source, a gate and a drain connected to electrode terminals, namely to a source terminal, a gate terminal and a drain terminal, respectively. The electrode terminals are connected to a potential uniformalizing terminal via potential uniformalizing wiring in order to uniform the potentials of the electrode terminals. When conducting a characteristic inspection, a voltage is applied across the electrode terminals and the potential uniformalizing terminal to melt the potential uniformalizing wiring.Type: ApplicationFiled: February 24, 2006Publication date: December 7, 2006Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Atsushi ENDO, Takumi NAKAHATA
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Patent number: 6828182Abstract: A method for selectively forming an epitaxial thin film on a semiconductor substrate by controlling a flow rate of a source gas supplied to a deposition ambient includes determining a relation between the growth rate of the epitaxial thin film and the gas flow rate by changing the flow rate of the gas supplied to the deposition ambient at a prescribed temperature. A mass transfer limited region, a kinetically limited region, and an intermediate region are identified. The method further includes supplying the source gas at the flow rate corresponding to the intermediate region to form the epitaxial thin film on the semiconductor substrate. Thus, a method for selectively forming a flat epitaxial thin film by controlling the growth temperature and the gas flow rate is provided.Type: GrantFiled: August 22, 2002Date of Patent: December 7, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takumi Nakahata
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Patent number: 6635938Abstract: A polysilicon nitride film is formed to cover a polysilicon gate. By heat treatment of the silicon nitride film in an oxygen atmosphere, a silicon oxinitride film is formed. By anisotropically etching the silicon oxinitride film and the silicon nitride film, a sidewall insulating film is formed. By epitaxial growth, selective silicon films of a prescribed film thickness are formed on source and drain regions. During this period, silicon islands are not deposited on the surface of sidewall insulating film. Consequently, a semiconductor device including a transistor of a superior electrical insulation can be obtained.Type: GrantFiled: November 21, 2000Date of Patent: October 21, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takumi Nakahata, Shigemitsu Maruno, Taisuke Furukawa, Naruhisa Miura, Toshiyuki Oishi, Yasunori Tokuda
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Publication number: 20030162365Abstract: The method for selectively forming an epitaxial thin film on a semiconductor substrate by controlling a flow rate of a gas material supplied to a deposition atmosphere includes the step of determining a relation between the growth rate of the epitaxial thin film and the gas flow rate by changing the flow rate of the gas supplied to the deposition atmosphere under a prescribed temperature condition. In this step, a mass transfer limited region, a kinetically limited region and an intermediate region are determined. The method further includes the step of supplying the gas material at the flow rate corresponding to the intermediate region to form the epitaxial thin film on the semiconductor substrate. Thus, the method for selectively forming a flat epitaxial thin film by controlling the growth temperature and the gas flow rate is provided.Type: ApplicationFiled: August 22, 2002Publication date: August 28, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Takumi Nakahata
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Patent number: 6465851Abstract: Epitaxial silicon layers are formed on n+-source/drain regions of two MOS transistors neighboring to each other and formed on a silicon substrate, respectively. In this processing, polycrystalline silicon pieces are generated on an element isolating and insulating film and others. Thereafter, the silicon substrate is exposed to an oxygen atmosphere so that hydrogen reacts with silicon at the surfaces of the epitaxial silicon layers and the surfaces of the polycrystalline silicon pieces to form silicon oxide films and polycrystalline silicon pieces. Thereby, short-circuit between MOS transistors in neighboring memory cells is prevented, and a semiconductor device has a high electrical reliability.Type: GrantFiled: October 9, 1997Date of Patent: October 15, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takumi Nakahata, Satoshi Yamakawa, Yuji Abe
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Publication number: 20020140019Abstract: A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.Type: ApplicationFiled: May 13, 2002Publication date: October 3, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takumi Nakahata, Satoshi Yamakawa, Yoshihiko Toyoda
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Patent number: 6417534Abstract: A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.Type: GrantFiled: September 23, 1998Date of Patent: July 9, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takumi Nakahata, Satoshi Yamakawa, Yoshihiko Toyoda
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Patent number: 6373108Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.Type: GrantFiled: March 1, 1999Date of Patent: April 16, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Satoshi Yamakawa, Yasunori Tokuda, Takumi Nakahata, Taisuke Furukawa, Shigemitsu Maruno