Patents by Inventor Takumi Nakahata

Takumi Nakahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020000622
    Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.
    Type: Application
    Filed: March 1, 1999
    Publication date: January 3, 2002
    Inventors: SATOSHI YAMAKAWA, YASUNORI TOKUDA, TAKUMI NAKAHATA, TAISUKE FURUKAWA, SHIGEMITSU MARUNO
  • Patent number: 6316320
    Abstract: Epitaxial silicon layers are formed on n+-source/drain regions of two MOS transistors neighboring to each other and formed on a silicon substrate, respectively. In this processing, polycrystalline silicon pieces are generated on an element isolating and insulating film and others. Thereafter, the silicon substrate is exposed to an oxygen atmosphere so that hydrogen reacts with silicon at the surfaces of the epitaxial silicon layers and the surfaces of the polycrystalline silicon pieces to form silicon oxide films and polycrystalline silicon pieces. Thereby, short-circuit between MOS transistors in neighboring memory cells is prevented, and a semiconductor device has a high electrical reliability.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: November 13, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takumi Nakahata, Satoshi Yamakawa, Yuji Abe
  • Publication number: 20010019142
    Abstract: A polysilicon film, a titanium silicide film and a titanium nitride film are formed in a storage node contact hole of a memory cell region, while a polysilicon film, a titanium silicide film and a titanium nitride film are formed in a bit line contact hole. In a peripheral circuit region, a peripheral circuit contact hole is formed in a silicon oxide film, and another peripheral circuit contact hole is formed in an interlayer insulation film and a silicon oxide film. Thus obtained are a semiconductor device reducing a leakage current, suppressing an electrical short and attaining a high-speed operation while readily forming each contact hole and a method of fabricating the same.
    Type: Application
    Filed: September 23, 1998
    Publication date: September 6, 2001
    Inventors: TAKUMI NAKAHATA, SATOSHI YAMAKAWA, YOSHIHIKO TOYODA
  • Patent number: 6232192
    Abstract: Source/drain diffusion regions are formed on the silicon substrate such that the source/drain diffusion regions sandwich a gate electrode from both sides on the silicon substrate. Sidewall oxide films are formed, one on each side surface of the gate electrode. Recessed portions are formed in the extension portions E beneath the sidewall oxide films. Source/drain electrodes are formed to fill the recessed portions. Thus, the sheet resistance of the respective regions including a pair of source/drain diffusion regions and source/drain electrodes is reduced, and a semiconductor device with a field-effect transistor having an improved current drivability is obtained.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: May 15, 2001
    Assignee: Mitubishi Denki Kabushiki Kaisha
    Inventors: Satoshi Yamakawa, Yasunori Tokuda, Takumi Nakahata, Taisuke Furukawa, Shigemitsu Maruno
  • Patent number: 6228728
    Abstract: According to the inventive method of fabricating a semiconductor device, a silicon substrate is exposed to an oxygen atmosphere of 600° C. to 900° C., for forming silicon oxide films on surfaces of epitaxial silicon layers and those of silicon fragments. Thus, a method of fabricating a semiconductor device capable of preventing electrodes thereof from shorting can be provided.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: May 8, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Taisuke Furukawa, Takumi Nakahata, Shigemitsu Maruno, Kohei Sugihara, Yasutaka Nishioka, Satoshi Yamakawa, Yasunori Tokuda