Patents by Inventor Takuo Kikuchi
Takuo Kikuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190319125Abstract: According to one embodiment, a semiconductor device includes first, second, and third semiconductor regions, first, second, and third electrodes, and a first insulating portion. The first semiconductor region includes first and second partial regions. A first direction from the second partial region toward the second semiconductor region crosses a second direction from the second region toward the first partial region. The third semiconductor region is provided between the second partial region and the second semiconductor region in the first direction. The first insulating portion includes a first insulating region provided between the third semiconductor region and the first electrode in the second direction, a second insulating region provided between the first partial region and the first electrode in the first direction, and a third insulating region provided between the first partial region and the first insulating region in the first direction.Type: ApplicationFiled: March 19, 2019Publication date: October 17, 2019Applicants: KABUSHIKI KAISHA TOSHIBA, Toshiba Electronic Devices & Storage CorporationInventor: Takuo KIKUCHI
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Publication number: 20180301529Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type having a first surface crossing a first direction; a first semiconductor region of a second conductivity type provided in the first semiconductor layer, and including first and second layers aligned in the first direction; a second semiconductor region of the second conductivity type electrically connected to the first semiconductor region, and having a portion provided between the first surface and the first semiconductor region; and a third semiconductor region of the first conductivity type having a portion provided between the first surface and the portion of the second semiconductor region. The semiconductor device further includes a control electrode provided on the second semiconductor region via a first insulating film; an electrode electrically connected to the second and third semiconductor regions; and a sidewall region provided between the first semiconductor region and the first semiconductor layer.Type: ApplicationFiled: December 27, 2017Publication date: October 18, 2018Applicant: Kabushiki Kaisha ToshibaInventor: Takuo KIKUCHI
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Patent number: 9966441Abstract: A semiconductor device, including a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap width larger than or equal to a band gap width of the first nitride semiconductor layer, first, second, and third electrodes provided on the second nitride semiconductor layer, an insulation layer provided on the second nitride semiconductor layer and between the first and second electrodes, and a conductor provided within the insulation layer between the second and third electrodes and connecting the second and third electrodes to each other, or the conductor provided within the insulation layer between the first and second electrodes and connecting the first and second electrodes to each other, the conductor including a plurality of conductive regions arranged in a first direction from the first electrode toward the second electrode, the conductive regions being electrically connected to one another.Type: GrantFiled: September 8, 2016Date of Patent: May 8, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Takuo Kikuchi, Yoshiro Baba, Masahiko Yamamoto
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Publication number: 20180076311Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.Type: ApplicationFiled: February 24, 2017Publication date: March 15, 2018Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasunobu SAITO, Kohei OASA, Takuo KIKUCHI, Junji KATAOKA, Tatsuya SHIRAISHI, Akira YOSHIOKA, Kazuo SAKI
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Patent number: 9917182Abstract: A semiconductor device includes: a first nitride semiconductor layer, a second nitride semiconductor layer that is provided on the first nitride semiconductor layer and has a band gap larger than a band gap of the first nitride semiconductor layer, a gate electrode that is provided on the first nitride semiconductor layer, a first electrode that is electrically connected to the first nitride semiconductor layer, a second electrode disposed such that the gate electrode is positioned between the first electrode and the second electrode, and electrically connected to the first nitride semiconductor layer, and a first insulation layer that is provided between the gate electrode and the second electrode, disposed such that the second nitride semiconductor layer is positioned between the first nitride semiconductor layer and the first insulation layer, and including silicon oxide having an oxygen-to-silicon atomic ratio (O/Si) of 1.50 or more and 1.85 or less.Type: GrantFiled: February 24, 2017Date of Patent: March 13, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasunobu Saito, Kohei Oasa, Takuo Kikuchi, Junji Kataoka, Tatsuya Shiraishi, Akira Yoshioka, Kazuo Saki
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Publication number: 20170271493Abstract: A semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer containing aluminum located on the first nitride semiconductor layer, a third nitride semiconductor layer with an aluminum concentration higher than that of the second nitride semiconductor layer located on the second nitride semiconductor layer, a drain electrode and a source electrode provided on one of the second nitride semiconductor layer and on the third nitride semiconductor layer, and a gate electrode located between the drain electrode and the source electrode.Type: ApplicationFiled: August 8, 2016Publication date: September 21, 2017Inventors: Akira YOSHIOKA, Takuo KIKUCHI, Junji KATAOKA, Naoharu SUGIYAMA, Hung HUNG, Yasuhiro ISOBE
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Publication number: 20170084704Abstract: A semiconductor device, including a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap width larger than or equal to a band gap width of the first nitride semiconductor layer, first, second, and third electrodes provided on the second nitride semiconductor layer, an insulation layer provided on the second nitride semiconductor layer and between the first and second electrodes, and a conductor provided within the insulation layer between the second and third electrodes and connecting the second and third electrodes to each other, or the conductor provided within the insulation layer between the first and second electrodes and connecting the first and second electrodes to each other, the conductor including-a plurality of conductive regions arranged in a first direction from the first electrode toward the second electrode, the conductive regions being electrically connected to one another.Type: ApplicationFiled: September 8, 2016Publication date: March 23, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Takuo KIKUCHI, Yoshiro BABA, Masahiko YAMAMOTO
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Patent number: 8854117Abstract: According to one embodiment, a semiconductor device includes: a substrate; a first circuit portion; and a second circuit portion. The first circuit portion includes: a first and a second switching elements, and a first and a second diodes. The second circuit portion includes a third and a fourth switching elements, and a third and a fourth diodes. The first switching element is juxtaposed with the second switching element in a first direction, and is juxtaposed with the fourth switching element in a second direction. The third switching element is juxtaposed with the fourth switching element in the first direction, and is juxtaposed with the second switching element in the second direction. A voltage is applied to electrodes of the first and third switching elements. A voltage of a polarity opposite the first voltage is applied to electrodes of the second and fourth switching elements.Type: GrantFiled: March 11, 2013Date of Patent: October 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazuto Takao, Hiroshi Kono, Takuo Kikuchi
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Publication number: 20140084993Abstract: According to one embodiment, a semiconductor device includes: a substrate; a first circuit portion; and a second circuit portion. The first circuit portion includes: a first and a second switching elements, and a first and a second diodes. The second circuit portion includes a third and a fourth switching elements, and a third and a fourth diodes. The first switching element is juxtaposed with the second switching element in a first direction, and is juxtaposed with the fourth switching element in a second direction. The third switching element is juxtaposed with the fourth switching element in the first direction, and is juxtaposed with the second switching element in the second direction. A voltage is applied to electrodes of the first and third switching elements. A voltage of a polarity opposite the first voltage is applied to electrodes of the second and fourth switching elements.Type: ApplicationFiled: March 11, 2013Publication date: March 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kazuto TAKAO, Hiroshi Kono, Takuo Kikuchi
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Publication number: 20130069035Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting layer, and an electron blocking layer. The light emitting layer is provided between the n-type semiconductor layer and the p-type semiconductor layer and includes a nitride semiconductor. The electron blocking layer is provided between the light emitting layer and the p-type semiconductor layer and has an aluminum composition ratio increasing from the light emitting layer toward the p-type semiconductor layer.Type: ApplicationFiled: September 14, 2012Publication date: March 21, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takuo KIKUCHI, Hidehiko YABUHARA, Chiyang CHANG
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Patent number: 8338820Abstract: According to one embodiment, a semiconductor light emitting device includes a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer. The first conductivity type layer has a superlattice structure. First semiconductor layers and second semiconductor layers are alternately provided in the superlattice structure. The first semiconductor layers include a first nitride semiconductor and the second semiconductor layers include a second nitride semiconductor having a larger lattice constant than the first nitride semiconductor. The light emitting layer has a multi-quantum well structure. Quantum well layers and barrier layers are alternately provided in the multi-quantum well structure. The quantum well layers include a third nitride semiconductor having a smaller lattice constant than the second nitride semiconductor and the barrier layers include a fourth nitride semiconductor having a smaller lattice constant than the third nitride semiconductor.Type: GrantFiled: August 11, 2011Date of Patent: December 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takuo Kikuchi, Hidehiko Yabuhara
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Publication number: 20120211724Abstract: According to an embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer provided between the n-type semiconductor layer and the p-type semiconductor layer. The light emitting layer includes at least one quantum well, and the quantum well adjacent to the p-type semiconductor layer includes a first barrier layer and a second barrier layer, the first barrier layer nearer to the p-type semiconductor layer being doped with p-type impurity.Type: ApplicationFiled: January 19, 2012Publication date: August 23, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Takuo KIKUCHI, Hidehiko Yabuhara
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Publication number: 20120056156Abstract: According to one embodiment, a semiconductor light emitting device includes a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer. The first conductivity type layer has a superlattice structure. First semiconductor layers and second semiconductor layers are alternately provided in the superlattice structure. The first semiconductor layers include a first nitride semiconductor and the second semiconductor layers include a second nitride semiconductor having a larger lattice constant than the first nitride semiconductor. The light emitting layer has a multi-quantum well structure. Quantum well layers and barrier layers are alternately provided in the multi-quantum well structure. The quantum well layers include a third nitride semiconductor having a smaller lattice constant than the second nitride semiconductor and the barrier layers include a fourth nitride semiconductor having a smaller lattice constant than the third nitride semiconductor.Type: ApplicationFiled: August 11, 2011Publication date: March 8, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Takuo KIKUCHI, Hidehiko YABUHARA
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Patent number: 7262511Abstract: The present invention provides a conductive adhesive agent capable of being diluted with a solvent to give good coating workability and allowing formation of a conductive joint excellent in both thermal conductivity and electrical conductivity by inhibiting a gas generated when a binder resin is heat-cured after attachment of a part. The conductive adhesive agent according to the present invention is a conductive adhesive agent wherein, based on 100 parts by weight of silver powder having an average particle diameter of micrometers, which is used for a conductive medium, e.g.Type: GrantFiled: August 18, 2005Date of Patent: August 28, 2007Assignees: Harima Chemicals, Inc., Toshiba CorporationInventors: Katsuhisa Osako, Naoto Shioi, Daisuke Itoh, Hideyuki Gotoh, Yorishige Matsuba, Kazuki Tateyama, Yasunari Ukita, Masao Segawa, Takuo Kikuchi
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Publication number: 20060038304Abstract: The present invention provides a conductive adhesive agent capable of being diluted with a solvent to give good coating workability and allowing formation of a conductive joint excellent in both thermal conductivity and electrical conductivity by inhibiting a gas generated when a binder resin is heat-cured after attachment of a part. The conductive adhesive agent according to the present invention is a conductive adhesive agent wherein, based on 100 parts by weight of silver powder having an average particle diameter of micrometers, which is used for a conductive medium, e.g.Type: ApplicationFiled: August 18, 2005Publication date: February 23, 2006Applicants: HARIMA CHEMICALS, INC., TOSHIBA CORPORATIONInventors: Katsuhisa Osako, Naoto Shioi, Daisuke Itoh, Hideyuki Gotoh, Yorishige Matsuba, Kazuki Tateyama, Yasunari Ukita, Masao Segawa, Takuo Kikuchi