Patents by Inventor TAKURO MURASE

TAKURO MURASE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200028017
    Abstract: A light-receiving element includes an on-chip lens; an interconnection layer; and a semiconductor layer that is disposed between the on-chip lens and the interconnection layer. The semiconductor layer includes a first voltage application unit to which a first voltage is applied, a second voltage application unit to which a second voltage different from the first voltage is applied, a first charge detection unit that is disposed at the periphery of the first voltage application unit, a second charge detection unit that is disposed at the periphery of the second voltage application unit, and a charge discharge region that is provided on an outer side of an effective pixel region. For example, the present technology is applicable to a light-receiving element that generates distance information in a ToF method, or the like.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 23, 2020
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: TSUTOMU IMOTO, YUJI ISOGAI, TAKUYA MARUYAMA, TAKURO MURASE, RYOTA WATANABE, TAKESHI YAMAZAKI
  • Patent number: 10256269
    Abstract: The present technology relates to a solid-state imaging element, an imaging device, and an electronic apparatus which enable enhancement of focusing accuracy and sensitivity and suppression of color mixing, in a high image height portion. Incident light is condensed by a main lens, and the condensed light is condensed by a plurality of on-chip lenses. The on-chip lenses are each shared by a plurality of photodiodes that receive the light condensed by the on-chip lens and that generate and accumulate electric charges corresponding to the amounts of light. The plurality of photodiodes sharing the on-chip lens are shaped, in accordance with the image height of the on-chip lens, in such a manner as to have substantially uniform light reception characteristics. The present technology is applicable to a CMOS image sensor.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: April 9, 2019
    Assignee: SONY CORPORATION
    Inventors: Takuro Murase, Hirotoshi Nomura
  • Publication number: 20180047775
    Abstract: The present technology relates to a solid-state imaging element, an imaging device, and an electronic apparatus which enable enhancement of focusing accuracy and sensitivity and suppression of color mixing, in a high image height portion. Incident light is condensed by a main lens, and the condensed light is condensed by a plurality of on-chip lenses. The on-chip lenses are each shared by a plurality of photodiodes that receive the light condensed by the on-chip lens and that generate and accumulate electric charges corresponding to the amounts of light. The plurality of photodiodes sharing the on-chip lens are shaped, in accordance with the image height of the on-chip lens, in such a manner as to have substantially uniform light reception characteristics. The present technology is applicable to a CMOS image sensor.
    Type: Application
    Filed: February 26, 2016
    Publication date: February 15, 2018
    Applicant: SONY CORPORATION
    Inventors: TAKURO MURASE, HIROTOSHI NOMURA