Abstract: To provide an imaging device capable of high-speed reading. The imaging device includes a photodiode, a first transistor, a second transistor, a third transistor, and a fourth transistor. The back gate electrode of the first transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the first transistor and a potential lower than the source potential of the first transistor. The back gate electrode of the second transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the second transistor. The back gate electrode of the third transistor is electrically connected to a wiring that can supply a potential higher than a source potential of the third transistor and a potential lower than the source potential of the third transistor.

Abstract: A dynamic logic circuit in which the number of elements is reduced, the layout area is reduced, the power loss is reduced, and the power consumption is reduced is provided. A semiconductor device including a dynamic logic circuit includes a first transistor in which a channel is formed in silicon and a second transistor in which a channel is formed in an oxide semiconductor. Here, a structure in which the second transistor is provided over the first transistor can be employed. A structure in which an insulating film is provided over the first transistor, and the second transistor is provided over the insulating film can be employed. A structure in which a top surface of the insulating film is planarized can be employed. A structure in which the second transistor has a region overlapping with the first transistor can be employed.

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract: Provided is a novel semiconductor device, a semiconductor device with reduced area, or a versatile semiconductor device. The semiconductor device includes a pixel portion including a first pixel, a second pixel, a third pixel, and a fourth pixel; a first switch and a second switch located outside the first to fourth pixels; a first wiring located outside the first to fourth pixels; a second wiring electrically connected to the first and second pixels; and a third wiring electrically connected to the third and fourth pixels. A first terminal of the first switch is electrically connected to the first wiring. A second terminal of the first switch is electrically connected to the second wiring. A first terminal of the second switch is electrically connected to the first wiring. A second terminal of the second switch is electrically connected to the third wiring.

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

Abstract: A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit.

Abstract: To reduce power consumption, a memory circuit includes a latch unit in which first data and second data are rewritten and read in accordance with a control signal, a first switch unit that controls rewrite and read of the first data stored in the latch unit by being turned on or off in response to the control signal, and a second switch unit that controls rewrite and read of the second data stored in the latch unit by being turned on or off in response to the control signal. The latch unit includes a first inverter and a second inverter. At least one of the first inverter and the second inverter includes a first field-effect transistor, and a second field-effect transistor that has the same conductivity type as the first field-effect transistor and has a gate potential controlled in accordance with the control signal.

Abstract: A semiconductor device includes a first latch, a second latch and a transistor whose semiconductor layer contains an oxide semiconductor. An input of the first latch is electrically connected to one of a source and a drain of the transistor, an output of the first latch is electrically connected to an input of the second latch, and an output of the second latch is electrically connected to the other of the source or the drain of the transistor.

Abstract: An imaging device includes a pixel; a digital circuit; and an analog processing circuit including a constant current circuit, a current comparison circuit, and a control circuit. The pixel is capable of outputting differential data. The constant current circuit is capable of supplying a first current corresponding to the differential data, in accordance with a first control signal. The current comparison circuit is capable of supplying a second current that flows through the constant current circuit in accordance with a change in the differential data. The current comparison circuit has a function of setting a determination signal active depending on whether to supply the second current to the constant current circuit. The control circuit has a function of controlling the constant current circuit and the current comparison circuit to stop their functions as the determination signal becomes active. The digital circuit operates as the determination signal becomes active.

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

Abstract: An imaging device with high productivity and improved dynamic range is provided. The imaging device includes a pixel driver circuit and a photoelectric conversion element including a p-type semiconductor, an n-type semiconductor, and an i-type semiconductor. In a plan view, the total area of a part of the i-type semiconductor overlapped with neither a metal material nor a semiconductor material constituting the pixel driver circuit is preferably greater than or equal to 65%, more preferably greater than or equal to 80%, and still more preferably greater than or equal to 90% of the area of the whole i-type semiconductor. Plural photoelectric conversion elements are provided in the same semiconductor, whereby a process for separating the photoelectric conversion elements can be omitted. The i-type semiconductors in the plural photoelectric conversion elements are separated from each other by the p-type semiconductor or the n-type semiconductor.

Abstract: A semiconductor device including a register controller and a processor which includes a register is provided. The register includes a first circuit and a second circuit which includes a plurality of memory portions. The first circuit and the plurality of memory portions can store data by an arithmetic process of the processor. Which of the plurality of memory portions the data is stored in depends on a routine by which the data is processed. The register controller switches the routine in response to an interrupt signal. The register controller can make any one of the plurality of memory portions which corresponds to the routine store the data in the first circuit every time the routine is switched. The register controller can make data stored in any one of the plurality of memory portions which corresponds to the routine be stored in the first circuit every time the routine is switched.

Abstract: A DC-DC converter includes a control circuit, a switching element, and a constant-voltage generation portion which generates an output voltage on the basis of an input voltage supplied through the switching element. The control circuit includes AD converters which convert the input voltage and the output voltage, a signal processing circuit, a pulse modulation circuit, and a power supply control circuit which controls supply of a power supply voltage to the signal processing circuit in accordance with digital values of the input voltage and the output voltage. The signal processing circuit determines the duty ratio in accordance with the digital value of the output voltage, and the pulse modulation circuit controls the switching element. The signal processing circuit includes a memory device including a memory element, a capacitor for storing data of the memory element, and a transistor for controlling charge in the capacitor. The transistor includes an oxide semiconductor.

Abstract: To provide a novel semiconductor device. The semiconductor device includes a circuit including a memory cell including a transistor using an oxide semiconductor; and a refresh timing determination unit including a capacitor, a transistor using an oxide semiconductor, and a comparator circuit. The potential of a floating node in the refresh timing determination unit is directly or indirectly input to the comparator circuit and compared with a reference potential. When the potential of the floating node becomes a certain value, a power switch operating in accordance with an output of the comparator circuit is turned on, power is supplied to the circuit including the memory cell, and then the reference potential is also changed. After that, refresh operation of the memory cell is performed. When the refresh operation is finished, the power switch is turned off.

Abstract: The present invention provides a memory circuit in which, while the power is not supplied, a data signal that has been held in a memory section corresponding to a volatile memory can be held in a capacitor in a memory section corresponding to a nonvolatile memory. In the nonvolatile memory section, a transistor whose channel is formed in an oxide semiconductor layer allows a signal to be held in the capacitor for a long period. Thus, the memory circuit can hold a logic state (data signal) even while the power supply is stopped. A potential applied to a gate of the transistor whose channel is formed in an oxide semiconductor layer is raised by a booster circuit provided between a wiring for carrying power supply potential and the gate of the transistor, allowing a data signal to be held even by one power supply potential without malfunction.

Abstract: To supply a signal in which the occurrence of delays is prevented to a storage circuit. To provide a novel semiconductor device in which a load applied to a logic circuit is low. The following structure is completed: a storage circuit to which a plurality of data signals and a selection signal are supplied connects two combination circuits, and a storage circuit has a function of selecting one of a plurality of data signals in accordance with the selection signal. A selection circuit is not necessarily provided between the storage circuit and the combination circuit. As a result, the combination circuit can supply a signal in which the occurrence of delays is prevented to the storage circuit.

Abstract: An object is to reduce degradation of circuit operation and to reduce the area of the entire circuit. A power source circuit is provided with a first terminal to which first voltage is input; a second terminal to which second voltage is input; a comparator being connected to the first terminal and the second terminal and comparing the first voltage and the second voltage; a digital circuit averaging, integrating, and digital pulse width modulating a first digital signal output from the comparator; a PWM output driver amplifying a second digital signal output from the digital circuit; and a smoothing circuit smoothing the amplified second digital signal.

Abstract: Provided is a memory device with reduced overhead power. A memory device includes a first circuit retaining data in a first period during which a power supply voltage is supplied; a second circuit saving the data retained in the first circuit in the first period and retaining the data saved from the first circuit in a second period during which the power supply voltage is not supplied; and a third circuit saving the data retained in the second circuit in the second period and retaining the data saved from the second circuit in a third period during which the power supply voltage is not supplied. The third circuit includes a transistor in which a channel formation region is provided in an oxide semiconductor film and a capacitor to which a potential corresponding to the data is supplied through the transistor.