Patents by Inventor Takushi Shigetoshi
Takushi Shigetoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096919Abstract: The present technology relates to a semiconductor device, an imaging device, and a manufacturing method capable of forming a via connected to wirings at different depths so as not to cause a defect. A plurality of vias is provided, and an aspect ratio defined by a depth and a width of the via is substantially the same in the plurality of vias. The via is connected to the wiring in the wiring layer constituting the chip. The plurality of vias includes a first via that penetrates a chip stacked in the wiring layer and a second via that does not penetrate the chip. The present technology can be applied to, for example, a chip on which a solid-state imaging element is formed and an imaging element in which other chips are stacked.Type: ApplicationFiled: January 6, 2022Publication date: March 21, 2024Inventor: TAKUSHI SHIGETOSHI
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Publication number: 20240055461Abstract: Provided are a semiconductor device capable of constituting a through electrode having a desired shape, an electronic device, and a method for manufacturing a semiconductor device. The semiconductor device includes: a first substrate including silicon; a first film formed on at least some surfaces of a hole-shaped portion formed in the first substrate; and a photosensitive second film covering at least a part of a side surface of the hole-shaped portion with the first film interposed therebetween.Type: ApplicationFiled: December 22, 2021Publication date: February 15, 2024Inventors: YOSHIAKI YANAGAWA, TAKUSHI SHIGETOSHI
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Publication number: 20240055326Abstract: In a semiconductor device provided with a through electrode, thermal stress is reduced. The semiconductor device includes a semiconductor substrate, a wiring layer, a first through hole, and a first inner through electrode. In the semiconductor device, the wiring layer is formed on a front surface of the semiconductor substrate. Furthermore, in the semiconductor device, the first through hole penetrates the semiconductor substrate from a back surface to the front surface of the semiconductor substrate, and has a side wall covered with an insulating film. Furthermore, in the semiconductor device, the first inner through electrode is formed along a part of the side wall of the first through hole.Type: ApplicationFiled: January 17, 2022Publication date: February 15, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takushi SHIGETOSHI, Yoshiaki YANAGAWA
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Publication number: 20240021498Abstract: A yield is improved in a semiconductor device in which a through electrode covered with an insulating film is formed. A semiconductor device includes a through electrode, an insulating film, and a wiring layer. In a semiconductor device including a through electrode, an insulating film, and a wiring layer, the through electrode penetrates the semiconductor substrate along a direction perpendicular to a predetermined front surface of the semiconductor substrate. Furthermore, the insulating film covers the through electrode. Moreover, the wiring layer includes a dummy gate disposed in a region between an outer periphery of the insulating film and an inner periphery of the insulating film on the front surface.Type: ApplicationFiled: October 14, 2021Publication date: January 18, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takushi SHIGETOSHI, Naoto SASAKI, Kenichi SAITOU
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Publication number: 20230361146Abstract: A semiconductor apparatus having multiple semiconductor chips stacked one on top of another improves functionality while reducing manufacturing costs. The semiconductor chips include a light-receiving chip, a rewiring-side semiconductor chip, an intermediate semiconductor chip, through-electrodes, and rewiring. The light-receiving chip receives incident light. A wiring layer is formed on a predetermined wiring surface of the rewiring-side semiconductor chip. One of a pair of bonding surfaces of the intermediate semiconductor chip is bonded to the light-receiving chip, and the other of the pair of bonding surfaces is bonded to the rewiring-side semiconductor chip. The through-electrodes penetrate a semiconductor substrate of the intermediate semiconductor chip. The rewiring is provided on the wiring surface in a manner connecting the through-electrodes with the wiring layer.Type: ApplicationFiled: July 7, 2021Publication date: November 9, 2023Inventor: TAKUSHI SHIGETOSHI
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Patent number: 11791210Abstract: Provided is a semiconductor device that includes a cylindrical insulating film, a front surface side pad, a conductor layer, and a back surface side pad. The cylindrical insulating film is configured in a cylindrical shape penetrating a semiconductor substrate. The front surface side pad is formed adjacent to a front surface of the semiconductor substrate inside the cylindrical insulating film. The conductor layer is arranged adjacent to the front surface side pad and an inner side of the cylindrical insulating film after removing the semiconductor substrate inside the cylindrical insulating film adjacent to the front surface side pad. The back surface side pad is arranged on a back surface of the semiconductor substrate and is connected to the front surface side pad via the conductor layer.Type: GrantFiled: March 16, 2022Date of Patent: October 17, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Takushi Shigetoshi
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Publication number: 20230102481Abstract: A decrease in an insulation resistance between a separation region at a boundary between pixels and a wiring layer is prevented. A light receiving element includes the pixels, the separation region, the wiring layer, and a wiring layer protective film. The pixels included in the light receiving element have photoelectric conversion units, each photoelectric conversion unit being disposed in a semiconductor substrate to perform photoelectric conversion of incident light. The separation region included in the light receiving element is disposed at a boundary between the photoelectric conversion units and separates the photoelectric conversion units from each other. The wiring layer included in the light receiving element is wired to the pixels. The wiring layer protective film included in the light receiving element is disposed between the separation region and the wiring layer to protect the wiring layer.Type: ApplicationFiled: February 10, 2021Publication date: March 30, 2023Inventors: KENZO ISHIBASHI, TAKANORI TADA, TAKUSHI SHIGETOSHI, JUNPEI YAMAMOTO
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Publication number: 20230056708Abstract: Please replace the currently pending Abstract with the following amended A parasitic capacitance of a wiring arranged on a back surface side of a semiconductor substrate is reduced. A semiconductor apparatus includes a semiconductor substrate, a back surface side wiring, a through wiring, and a separation region. In the semiconductor substrate, a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side. The back surface side wiring is arranged on a back surface side of the semiconductor substrate. The through wiring is arranged in a through hole formed in the semiconductor substrate to connect the front surface side wiring and the back surface side wiring. The separation region is arranged between the semiconductor substrate and the back surface side wiring.Type: ApplicationFiled: February 15, 2021Publication date: February 23, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Naoto SASAKI, Kenichi SAITOU, Yusuke HAYASHI, Atsuhiko YAMADA, Takushi SHIGETOSHI, Takuya OOI
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Publication number: 20220406832Abstract: The sensitivity of an image sensor is improved. The image sensor includes a plurality of pixels and a light-blocking wall. The plurality of pixels included in the image sensor each includes a photoelectric conversion unit disposed on a semiconductor substrate and photoelectrically converting incident light that is irradiated, and an on-chip lens that focuses the incident light onto the photoelectric conversion unit. The light-blocking wall included in the image sensor is disposed adjacent to the semiconductor substrate at a boundary between the plurality of pixels and configured such that a side of the light-blocking wall that is irradiated with the incident light has a tapered-shape cross-section, the light-blocking wall blocking the incident light.Type: ApplicationFiled: September 15, 2020Publication date: December 22, 2022Inventors: HIROSHI TANAKA, YUSUKE MORIYA, TAKUSHI SHIGETOSHI
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Publication number: 20220344390Abstract: To reduce a dark current of an image sensor including a photoelectric conversion unit disposed on a back surface of a semiconductor substrate. The image sensor includes a photoelectric conversion unit, a through-electrode, a charge holding unit, a back-side high impurity concentration region, and a front-side high impurity concentration region. The photoelectric conversion unit is disposed on a back surface of a semiconductor substrate and performs photoelectric conversion of incident light. The through-electrode is formed in a shape penetrating from the back surface to a front surface of the semiconductor substrate and transmits a charge generated by the photoelectric conversion. The charge holding unit is disposed on the front surface of the semiconductor substrate and holds the transmitted charge.Type: ApplicationFiled: July 27, 2020Publication date: October 27, 2022Inventors: Akira FURUKAWA, Sho NISHIDA, Hideaki TOGASHI, Takushi SHIGETOSHI, Shinpei FUKUOKA, Junpei YAMAMOTO
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Publication number: 20220262842Abstract: To suppress variation in transistor characteristics due to charging damage to relieve restrictions on design necessary for avoiding the charging damage and improve the degree of freedom in design for increasing semiconductor integration. A semiconductor device includes a vertical electrode formed in a vertical hole extending from an opening portion toward a portion to be connected in a thickness direction of a base, and having a structure in which a barrier metal film and a conductive material are stacked sequentially from a side close to an insulating film exposed to the vertical hole, and a low-resistance film provided to lie between the barrier metal film and the insulating film except a vicinity of the portion to be connected, and having a lower resistance value than a resistance value of the insulating film.Type: ApplicationFiled: May 4, 2022Publication date: August 18, 2022Inventor: TAKUSHI SHIGETOSHI
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Patent number: 11380584Abstract: Damage to a semiconductor device at the time of forming a via hole in which a through electrode is arranged is prevented. The semiconductor device includes a cylindrical insulating film, a front surface side pad, a conductor layer, and a back surface side pad. The cylindrical insulating film is configured in a cylindrical shape penetrating a semiconductor substrate. The front surface side pad is formed adjacent to a front surface of the semiconductor substrate inside the cylindrical insulating film. The conductor layer is arranged adjacent to the front surface side pad and an inner side of the cylindrical insulating film after removing the semiconductor substrate inside the cylindrical insulating film adjacent to the front surface side pad. The back surface side pad is arranged on a back surface of the semiconductor substrate and is connected to the front surface side pad via the conductor layer.Type: GrantFiled: December 28, 2018Date of Patent: July 5, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Takushi Shigetoshi
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Publication number: 20220208608Abstract: Provided is a semiconductor device that includes a cylindrical insulating film, a front surface side pad, a conductor layer, and a back surface side pad. The cylindrical insulating film is configured in a cylindrical shape penetrating a semiconductor substrate. The front surface side pad is formed adjacent to a front surface of the semiconductor substrate inside the cylindrical insulating film. The conductor layer is arranged adjacent to the front surface side pad and an inner side of the cylindrical insulating film after removing the semiconductor substrate inside the cylindrical insulating film adjacent to the front surface side pad. The back surface side pad is arranged on a back surface of the semiconductor substrate and is connected to the front surface side pad via the conductor layer.Type: ApplicationFiled: March 16, 2022Publication date: June 30, 2022Inventor: TAKUSHI SHIGETOSHI
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Patent number: 11335720Abstract: To suppress variation in transistor characteristics due to charging damage to relieve restrictions on design necessary for avoiding the charging damage and improve the degree of freedom in design for increasing semiconductor integration. A semiconductor device includes a vertical electrode formed in a vertical hole extending from an opening portion toward a portion to be connected in a thickness direction of a base, and having a structure in which a barrier metal film and a conductive material are stacked sequentially from a side close to an insulating film exposed to the vertical hole, and a low-resistance film provided to lie between the barrier metal film and the insulating film except a vicinity of the portion to be connected, and having a lower resistance value than a resistance value of the insulating film.Type: GrantFiled: November 13, 2017Date of Patent: May 17, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Takushi Shigetoshi
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Patent number: 11282884Abstract: There is provided an imaging device with a semiconductor substrate having a first side and a second side opposite the first side. A photoelectric conversion unit is on the first side of the semiconductor substrate. A multilayer wiring layer is on the second side of the semiconductor substrate. A through electrode extends between the photoelectric conversion unit and the multilayer wiring layer. The multilayer wiring layer includes a local wiring layer. A second end of the through electrode is in direct contact with the local wiring layer.Type: GrantFiled: December 14, 2017Date of Patent: March 22, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Junpei Yamamoto, Takushi Shigetoshi, Takanori Tada, Shinpei Fukuoka
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Publication number: 20220085110Abstract: A solid-state imaging element according to the present disclosure includes one or more photoelectric conversion layers, a penetrating electrode, and a connection pad. The one or more photoelectric conversion layers are provided on one principal surface side serving as a light incidence plane of a semiconductor substrate. The penetrating electrode is provided in a pixel area, connected at one end to the photoelectric conversion layer to penetrate through front and back surfaces of the semiconductor substrate, and transfers an electric charge photoelectrically converted by the photoelectric conversion layer, to a different principal surface side of the semiconductor substrate. The connection pad is provided on a same layer as gates (Ga, Gr, G1, and g2) of transistors (AMP, RST, TG1, and TG2) provided on the different principal surface side of the semiconductor substrate, and to which a different end of the penetrating electrode is connected.Type: ApplicationFiled: January 21, 2020Publication date: March 17, 2022Applicants: SONY GROUP CORPORATION, SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Takushi SHIGETOSHI, Hideaki TOGASHI, Junpei YAMAMOTO, Shinpei FUKUOKA, Moe TAKEO, Sho NISHIDA
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Publication number: 20210273006Abstract: An imaging element according to an embodiment of the present disclosure includes: a semiconductor substrate; a first photoelectric converter; a through electrode; a first dielectric film; and a second dielectric film. The semiconductor substrate has one surface and another surface that are opposed to each other. The semiconductor substrate has a through hole penetrating between the one surface and the other surface. The first photoelectric converter is provided above the one surface of the semiconductor substrate. The through electrode is electrically coupled to the first photoelectric converter. The through electrode penetrates the semiconductor substrate inside the through hole. The first dielectric film is provided on the one surface of the semiconductor substrate. The first dielectric film has first film thickness. The second dielectric film is provided on a side surface of the through hole. The second dielectric film has second film thickness.Type: ApplicationFiled: July 1, 2019Publication date: September 2, 2021Inventors: HIDEAKI TAGASHI, MOE TAKEO, SHO NISHIDA, JUNPEI YAMAMOTO, SHINPEI FUKUOKA, TAKUSHI SHIGETOSHI
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Publication number: 20210273008Abstract: A solid-state image sensor is provided that includes a semiconductor substrate, a charge accumulator disposed in the semiconductor substrate and configured to accumulate charge, a photoelectric converter provided above the semiconductor substrate and configured to convert light to charge, and a through electrode passing through the semiconductor substrate and electrically connecting the charge accumulator with the photoelectric converter. At an end portion on the photoelectric converter side of the through electrode, a cross-sectional area of a conductor positioned at the center of the through electrode in a cut section orthogonal to a through direction of the through electrode gradually increases toward the photoelectric converter along the through direction.Type: ApplicationFiled: July 23, 2019Publication date: September 2, 2021Applicants: SONY CORPORATION, SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Shinpei FUKUOKA, Moe TAKEO, Sho NISHIDA, Hideaki TOGASHI, Takushi SHIGETOSHI, Junpei YAMAMOTO
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Publication number: 20210217623Abstract: The present invention aims to improve the accuracy and stability when removing an insulating film at a bottom of a TSV to allow a through hole to open toward a connection target electrode. A semiconductor device manufacturing method including: forming a through hole in a semiconductor substrate by using anisotropic etching performed from a first surface side of the semiconductor substrate; forming a thin film being an insulating film on an entire inner surface of the through hole; forming a carbon-containing thin film using plasma deposition on the first surface including an opening edge portion of the through hole; engraving an inner bottom of the through hole by using anisotropic plasma etching with the carbon-containing thin film as a mask; removing the carbon-containing thin film by ashing; and forming a through-substrate electrode in the through hole.Type: ApplicationFiled: January 29, 2021Publication date: July 15, 2021Applicant: SONY CORPORATIONInventors: Takushi SHIGETOSHI, Takanori TADA
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Patent number: 10930516Abstract: The present invention aims to improve the accuracy and stability when removing an insulating film at a bottom of a TSV to allow a through hole to open toward a connection target electrode. A semiconductor device manufacturing method including: forming a through hole in a semiconductor substrate by using anisotropic etching performed from a first surface side of the semiconductor substrate; forming a thin film being an insulating film on an entire inner surface of the through hole; forming a carbon-containing thin film using plasma deposition on the first surface including an opening edge portion of the through hole; engraving an inner bottom of the through hole by using anisotropic plasma etching with the carbon-containing thin film as a mask; removing the carbon-containing thin film by ashing; and forming a through-substrate electrode in the through hole.Type: GrantFiled: May 8, 2017Date of Patent: February 23, 2021Assignee: Sony CorporationInventors: Takushi Shigetoshi, Takanori Tada