Patents by Inventor Takushi Shigetoshi

Takushi Shigetoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930516
    Abstract: The present invention aims to improve the accuracy and stability when removing an insulating film at a bottom of a TSV to allow a through hole to open toward a connection target electrode. A semiconductor device manufacturing method including: forming a through hole in a semiconductor substrate by using anisotropic etching performed from a first surface side of the semiconductor substrate; forming a thin film being an insulating film on an entire inner surface of the through hole; forming a carbon-containing thin film using plasma deposition on the first surface including an opening edge portion of the through hole; engraving an inner bottom of the through hole by using anisotropic plasma etching with the carbon-containing thin film as a mask; removing the carbon-containing thin film by ashing; and forming a through-substrate electrode in the through hole.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: February 23, 2021
    Assignee: Sony Corporation
    Inventors: Takushi Shigetoshi, Takanori Tada
  • Publication number: 20200402854
    Abstract: Damage to a semiconductor device at the time of forming a via hole in which a through electrode is arranged is prevented. The semiconductor device includes a cylindrical insulating film, a front surface side pad, a conductor layer, and a back surface side pad. The cylindrical insulating film is configured in a cylindrical shape penetrating a semiconductor substrate. The front surface side pad is formed adjacent to a front surface of the semiconductor substrate inside the cylindrical insulating film. The conductor layer is arranged adjacent to the front surface side pad and an inner side of the cylindrical insulating film after removing the semiconductor substrate inside the cylindrical insulating film adjacent to the front surface side pad. The back surface side pad is arranged on a back surface of the semiconductor substrate and is connected to the front surface side pad via the conductor layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: December 24, 2020
    Inventor: TAKUSHI SHIGETOSHI
  • Publication number: 20200083273
    Abstract: To suppress variation in transistor characteristics due to charging damage to relieve restrictions on design necessary for avoiding the charging damage and improve the degree of freedom in design for increasing semiconductor integration. A semiconductor device includes a vertical electrode formed in a vertical hole extending from an opening portion toward a portion to be connected in a thickness direction of a base, and having a structure in which a barrier metal film and a conductive material are stacked sequentially from a side close to an insulating film exposed to the vertical hole, and a low-resistance film provided to lie between the barrier metal film and the insulating film except a vicinity of the portion to be connected, and having a lower resistance value than a resistance value of the insulating film.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 12, 2020
    Inventor: TAKUSHI SHIGETOSHI
  • Publication number: 20190326345
    Abstract: There is provided an imaging device with a semiconductor substrate having a first side and a second side opposite the first side. A photoelectric conversion unit is on the first side of the semiconductor substrate. A multilayer wiring layer is on the second side of the semiconductor substrate. A through electrode extends between the photoelectric conversion unit and the multilayer wiring layer. The multilayer wiring layer includes a local wiring layer. A second end of the through electrode is in direct contact with the local wiring layer.
    Type: Application
    Filed: December 14, 2017
    Publication date: October 24, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Junpei YAMAMOTO, Takushi SHIGETOSHI, Takanori TADA, Shinpei FUKUOKA
  • Publication number: 20190198337
    Abstract: The present invention aims to improve the accuracy and stability when removing an insulating film at a bottom of a TSV to allow a through hole to open toward a connection target electrode. A semiconductor device manufacturing method including: forming a through hole in a semiconductor substrate by using anisotropic etching performed from a first surface side of the semiconductor substrate; forming a thin film being an insulating film on an entire inner surface of the through hole; forming a carbon-containing thin film using plasma deposition on the first surface including an opening edge portion of the through hole; engraving an inner bottom of the through hole by using anisotropic plasma etching with the carbon-containing thin film as a mask; removing the carbon-containing thin film by ashing; and forming a through-substrate electrode in the through hole.
    Type: Application
    Filed: May 8, 2017
    Publication date: June 27, 2019
    Applicant: SONY CORPORATION
    Inventors: Takushi SHIGETOSHI, Takanori TADA
  • Patent number: 10090296
    Abstract: A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: October 2, 2018
    Assignee: Sony Corporation
    Inventor: Takushi Shigetoshi
  • Publication number: 20180130743
    Abstract: A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 10, 2018
    Inventor: Takushi Shigetoshi
  • Patent number: 9865549
    Abstract: A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: January 9, 2018
    Assignee: Sony Corporation
    Inventor: Takushi Shigetoshi
  • Publication number: 20150097258
    Abstract: A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 9, 2015
    Inventor: Takushi Shigetoshi