Abstract: The present invention provides to a compound having an ACC inhibitory action, which is useful as an agent for the prophylaxis or treatment of obesity, diabetes, hypertension, hyperlipidemia, cardiac failure, diabetic complications, metabolic syndrome, sarcopenia, cancer and the like, and has superior efficacy. The present invention relates to a compound represented by the formula (I): wherein each symbol is as defined in the specification.

Abstract: The present invention provides a compound having an ACC inhibitory action, which is useful as an agent for the prophylaxis or treatment of obesity, diabetes and the like, and having superior efficacy. The present invention relates to a compound represented by the formula (I): wherein each symbol is as defined in the specification, or a salt thereof.

Abstract: The present invention provides to a compound having an ACC inhibitory action, which is useful as an agent for the prophylaxis or treatment of obesity, diabetes, hypertension, hyperlipidemia, cardiac failure, diabetic complications, metabolic syndrome, sarcopenia, cancer and the like, and has superior efficacy. The present invention relates to a compound represented by the formula (I): wherein each symbol is as defined in the specification.

Abstract: The present invention provides a compound represented by the formula: wherein the symbols are as described in the specification, or a salt thereof, which is useful for preventing/treating eicosanoid-associated diseases such as atherosclerosis, diabetes, obesity, atherothrombosis, asthma, fever, pain, cancer, rheumatism, osteoarthritis and atopic dermatitis, and which has an excellent pharmacological action, physicochemical properties, etc.

Abstract: A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.

Abstract: A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects commonly the control gates of the first MOS transistors in a same row. The first charge pump circuit is activated and generates a first voltage in a write operation and erase operation. The first voltage is supplied with either the well region or the word lines. The discharge circuit, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage.

Abstract: A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

Abstract: A headlamp for a bicycle includes an LED element, a power supply device supplying electric power to the LED element, a vibration sensor detecting vibration, a luminance detector detecting ambient illuminance, and a switching device providing ON-OFF control of electrical connection between the LED element and the power supply device in response to a result detected by the vibration sensor and a result detected by the illuminance detector. The vibration sensor has a helical spring and a central metal conductive wire passing through the helical spring, and the helical spring and the conductive wire are disposed to extend in a direction obliquely intersecting with a horizontal direction and a vertical direction when the headlamp is attached.

Abstract: A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. The first MOS transistors are connected commonly to the write bit lines and read bit lines. The latch circuits are provided for the write bit lines and hold write data for the memory cells. The n-channel MOS transistor transfer “1” data to the latch circuits in a data latch operation. The voltage setting circuits supply a potential corresponding to “0” data to the write bit lines in a read operation. In a data latch operation, the latch circuit corresponding to the write bit line connected to the memory cell into which “0” data is to be written latches the potential supplied to the write bit lines in a read operation.

Abstract: An illumination apparatus is provided that can achieve light distribution towards the front, and light illumination in a direction other than the front direction, without using a light source other than the light source for frontward illumination. The illumination apparatus includes a light emitting diode located at the front side of the illumination apparatus, corresponding to one end, a side transmission unit having a surface exposed at a gap in the casing, located rearward of the light emitting diode to transmit light from the side, and a light path modification unit, located rearward of the light emitting diode to modify the direction of light output from the light emitting diode towards the side transmission unit.

Abstract: A semiconductor memory device includes a memory cell array, word lines, bit lines, a control circuit, and a measurement circuit. The memory cell array has memory cells including a floating gate. The control circuit performs first control to collectively shift the threshold voltages of the memory cells to within a predetermined range with a first level as an upper limit, second control to shift a lower limit of the threshold voltages toward a second level lower than the first level, and third control to shift the lower limit to a third level. The measurement circuit measures the elapsed time from the start of the second control. The control circuit repeats the second control, and then terminates the second control when the lower limit reaches the second level or the elapsed time measured by the measurement circuit reaches the predetermined time and performing the third control.

Abstract: A semiconductor memory device including: a first memory cell array including a plurality of memory cells, a first switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the first memory cell array, a latch circuit for latching the data transferred from the first switch circuit, a first write selector circuit for transferring the data transferred from the latch circuit, a first bit line connected to at least one of the plurality of memory cells and receiving the data transferred from the first write selector circuit, a second memory cell array including a plurality of memory cells that are different from the plurality of memory cells arranged in the first memory cell array, a second switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the second memory cell array, a second write selector circuit connected to the second switch circuit and transferring the data transferred from the second swi

Abstract: A semiconductor memory device comprising: a first memory cell array including a plurality of memory cells, a first switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the first memory cell array, a latch circuit for latching the data transferred from the first switch circuit, a first write selector circuit for transferring the data transferred from the latch circuit, a first bit line connected to at least one of the plurality of memory cells and receiving the data transferred from the first write selector circuit, a second memory cell array including a plurality of memory cells that are different from the plurality of memory cells arranged in the first memory cell array, a second switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the second memory cell array, a second write selector circuit connected to the second switch circuit and transferring the data transferred from the second sw

Abstract: A semiconductor memory device includes memory cells, write bit lines, read bit lines, latch circuits, a n-channel MOS transistor, and voltage setting circuits. The memory cell includes a first MOS transistor having a charge accumulation layer and a control gate. The first MOS transistors are connected commonly to the write bit lines and read bit lines. The latch circuits are provided for the write bit lines and hold write data for the memory cells. The n-channel MOS transistor transfer “1” data to the latch circuits in a data latch operation. The voltage setting circuits supply a potential corresponding to “0” data to the write bit lines in a read operation. In a data latch operation, the latch circuit corresponding to the write bit line connected to the memory cell into which “0” data is to be written latches the potential supplied to the write bit lines in a read operation.

Abstract: A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects commonly the control gates of the first MOS transistors in a same row. The first charge pump circuit is activated and generates a first voltage in a write operation and erase operation. The first voltage is supplied with either the well region or the word lines. The discharge circuit, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage.

Abstract: A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

Abstract: A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.

Abstract: A semiconductor memory device includes a memory cell array, word lines, bit lines, a control circuit, and a measurement circuit. The memory cell array has memory cells including a floating gate. The control circuit performs first control to collectively shift the threshold voltages of the memory cells to within a predetermined range with a first level as an upper limit, second control to shift a lower limit of the threshold voltages toward a second level lower than the first level, and third control to shift the lower limit to a third level. The measurement circuit measures the elapsed time from the start of the second control. The control circuit repeats the second control, and then terminates the second control when the lower limit reaches the second level or the elapsed time measured by the measurement circuit reaches the predetermined time and performing the third control.

Abstract: An illumination apparatus is provided that can achieve light distribution towards the front, and light illumination in a direction other than the front direction, without using a light source other than the light source for frontward illumination. The illumination apparatus includes a light emitting diode located at the front side of the illumination apparatus, corresponding to one end, a side transmission unit having a surface exposed at a gap in the casing, located rearward of the light emitting diode to transmit light from the side, and a light path modification unit, located rearward of the light emitting diode to modify the direction of light output from the light emitting diode towards the side transmission unit.

Abstract: A sound absorbing structure including a sound absorbing member, an air layer, and a resonant sound absorbing structure. The air layer is formed in the rear of the sound absorbing member. The resonant sound absorbing structure includes a slit and is formed in the rear of the sound absorbing member. The sound absorbing member is a surface plate covering the rear air layer and the resonant sound absorbing structure, and the sound absorbing member is shaped in one of a plate and plane.