Patents by Inventor Takuya Hirota
Takuya Hirota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100103756Abstract: A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.Type: ApplicationFiled: October 22, 2009Publication date: April 29, 2010Applicant: NEC Electronics CorporationInventors: Takuya HIROTA, Takao Yanagida
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Patent number: 7692988Abstract: A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.Type: GrantFiled: July 8, 2008Date of Patent: April 6, 2010Assignee: NEC Electronics CorporationInventors: Takao Yanagida, Takuya Hirota
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Patent number: 7684270Abstract: In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD?Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.Type: GrantFiled: August 23, 2007Date of Patent: March 23, 2010Assignee: NEC Electronics CorporationInventors: Takuya Hirota, Takao Yanagida, Hiroyuki Takahashi
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Patent number: 7663945Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.Type: GrantFiled: October 12, 2007Date of Patent: February 16, 2010Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takuya Hirota, Atsushi Nakagawa
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Patent number: 7489576Abstract: A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.Type: GrantFiled: March 22, 2007Date of Patent: February 10, 2009Assignee: NEC Electronics CorporationInventors: Takuya Hirota, Takao Yanagida
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Publication number: 20090016123Abstract: A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.Type: ApplicationFiled: July 8, 2008Publication date: January 15, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Takao Yanagida, Takuya Hirota
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Patent number: 7466609Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.Type: GrantFiled: July 31, 2007Date of Patent: December 16, 2008Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takuya Hirota, Atsushi Nakagawa
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Publication number: 20080056031Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.Type: ApplicationFiled: October 12, 2007Publication date: March 6, 2008Inventors: Hiroyuki Takahashi, Takuya Hirota, Atsushi Nakagawa
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Publication number: 20080049530Abstract: In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD?Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.Type: ApplicationFiled: August 23, 2007Publication date: February 28, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Takuya Hirota, Takao Yanagida, Hiroyuki Takahashi
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Publication number: 20070280025Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.Type: ApplicationFiled: July 31, 2007Publication date: December 6, 2007Inventors: Hiroyuki Takahashi, Takuya Hirota, Atsushi Nakagawa
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Patent number: 7301830Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.Type: GrantFiled: September 10, 2004Date of Patent: November 27, 2007Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takuya Hirota, Atsushi Nakagawa
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Patent number: 7277344Abstract: A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory cells based on a timer period, which sets the timer period in accordance with a disturb amount in an active mode upon shift from the active mode to the standby mode.Type: GrantFiled: February 24, 2006Date of Patent: October 2, 2007Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takuya Hirota
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Publication number: 20070223297Abstract: A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.Type: ApplicationFiled: March 22, 2007Publication date: September 27, 2007Applicant: NEC ELECTRONICS CORPORATIONInventors: Takuya Hirota, Takao Yanagida
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Patent number: 7203113Abstract: Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.Type: GrantFiled: March 28, 2005Date of Patent: April 10, 2007Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takato Shimoyama, Takuya Hirota
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Patent number: 7184322Abstract: A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.Type: GrantFiled: November 12, 2004Date of Patent: February 27, 2007Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takato Shimoyama, Takuya Hirota
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Publication number: 20060198226Abstract: A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lines to refresh each of the plurality of memory cells based on a timer period, which sets the timer period in accordance with a disturb amount in an active mode upon shift from the active mode to the standby mode.Type: ApplicationFiled: February 24, 2006Publication date: September 7, 2006Applicant: NEC ELECTRONICS CORPORATIONInventors: Hiroyuki Takahashi, Takuya Hirota
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Patent number: 7054223Abstract: A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.Type: GrantFiled: August 18, 2004Date of Patent: May 30, 2006Assignee: NEC Electronics CorporationInventors: Hiroyuki Takahashi, Takuya Hirota
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Patent number: 7006401Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.Type: GrantFiled: December 25, 2002Date of Patent: February 28, 2006Assignee: NEC Electronics Corp.Inventors: Hiroyuki Takahashi, Takuya Hirota, Noriaki Komatsu, Atsushi Nakagawa, Susumu Takano, Masahiro Yoshida, Yuuji Torige, Hideo Inaba
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Publication number: 20050237848Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.Type: ApplicationFiled: September 10, 2004Publication date: October 27, 2005Inventors: Hiroyuki Takahashi, Takuya Hirota, Atsushi Nakagawa
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Publication number: 20050219930Abstract: Disclosed is a semiconductor storage device in which control is performed in such a manner that if the refresh operation is not being performed when a chip-select signal undergoes a transition from an inactive (standby) state to an active state, read or write access is executed immediately and if the refresh operation is in progress when the chip-select signal undergoes a transition from the inactive state to the active state, a wait signal for causing read or write access to wait is generated by a wait generating circuit.Type: ApplicationFiled: March 28, 2005Publication date: October 6, 2005Inventors: Hiroyuki Takahashi, Takato Shimoyama, Takuya Hirota