Abstract: A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

Abstract: A semiconductor memory device has common terminals shared between a part or all of address terminals for receiving n bits of an address signal and data terminals for outputting a data signal with its bit width of n bits or less and dedicated address terminals for receiving m bits of the address signal, wherein at the time of a read, after the n bits of the address signal have been input, a plurality of data signals within a selected page are consecutively read out through the common terminals using the m bits of the address signal input from the dedicated address terminals.

Abstract: Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

Abstract: A semiconductor memory device adapted for avoiding collision between the selection period of a word line for a refresh and the selection period of a word line for a read/write, comprises a cell array including a plurality of memory cells that require refreshing for retention of storage data and means for exercising control so that when a read/write request is input in a clock cycle following a clock cycle for performing a refresh operation, a read/write operation in the cell array is delayed by at least one clock cycle, and the read/write operation is started after completion of the refresh.

Abstract: A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

Abstract: A semiconductor memory device, capable of being accessed at a high speed, according to the present invention, is provided, and is configured with the changeover point in time between the pre-charge operation and a word line selection operation on the far-end side of the sense amplifier being earlier than that on the near-end side of it. There are provided word selection signal input buffer, block selection signal input buffer, digit selection signal input buffer on semiconductor chip, decoders, which decode the said signals, drivers for the output signal of each decoder, memory block, which is stored with information, and gate circuit, which selects a column of memory cells in a memory block. Drivers for the word selection signal and block selection signal are laid out in the middle of chip and near far-end side pre-charge unit, which is located the farthest from the sense amplifier (which is deployed in near-end side pre-charge unit.

Abstract: A semiconductor chip has a first ground line for maintaining a stable ground potential for the internal circuit. The first ground line is connected to a second ground line disposed on a scribe region of the semiconductor chip via a bonding pad, which is connected to an external lead frame. I/O circuit has a third ground line directly connected to the second ground line without passing the bonding pad. The noise propagated from the third ground line to the first ground line is reduced by passing the noise through the bonding pad.

Abstract: A semiconductor memory device, capable of being accessed at a high speed, according to the present invention, is provided, and is configured with the changeover point in time between the pre-charge operation and a word line selection operation on the far-end side of the sense amplifier being earlier than that on the near-end side of it. There are provided word selection signal input buffer, block selection signal input buffer, digit selection signal input buffer on semiconductor chip, decoders, which decode the said signals, drivers for the output signal of each decoder, memory block, which is stored with information, and gate circuit, which selects a column of memory cells in a memory block. Drivers for the word selection signal and block: selection signal are laid out in the middle of chip and near far-end side pre-charge unit, which is located the farthest from the sense amplifier (which is deployed in near-end side pre-charge unit.

Abstract: A semiconductor storage device is disclosed that can lower sense amplifier input potentials to about a half supply potential (VCC/2) to speed up sense amplifier operations. According to one embodiment, a semiconductor storage device (100) may include a pair of digit lines (104 and 106), a memory cell (108) that can place stored data on digit lines (104 and 106), a sense amplifier (112) that may read memory cell data on digit lines (104 and 106), and switching devices (120-a and 120-b) connected between sense amplifier inputs (112-a and 112-b) and digit lines (104 and 106). Digit lines (104 and 106) may be precharged to a high potential. Memory cell data may then be placed on the digit lines (104 and 106). Prior to the activation of the sense amplifier (112) switching devices (120-a and 120-b) may lower the digit line potentials to a level more conducive to sensing by the sense amplifier (112). In this way, a read operation by the sense amplifier (112) may be faster than conventional approaches.

Abstract: A pulse duration changer generates an output pulse signal longer in pulse duration than an input pulse signal, wherein the pulse duration changer firstly produces a first control pulse signal synchronous with the input pulse signal and shorter in pulse duration than the input pulse signal, thereafter, produces a second control pulse signal synchronous with the first control pulse signal and longer in pulse duration than the input pulse signal, and finally defines the pulse duration of a preliminary output pulse signal as long as the second control pulse signal, thereby keeping the pulse duration of the output signal constant when the input pulse signal has an ultra high frequency.

Abstract: A semiconductor chip has a first ground line for maintaining a stable ground potential for the internal circuit. The first ground line is connected to a second ground line disposed on a scribe region of the semiconductor chip via a bonding pad, which is connected to an external lead frame. I/O circuit has a third ground line directly connected to the second ground line without passing the bonding pad. The noise propagated from the third ground line to the first ground line is reduced by passing the noise through the bonding pad.

Abstract: A data latch circuit includes a differential amplifier for detecting a potential difference between a pair of signal transmission lines for transmitting a pair of complementary signals, a latch timing signal generator for generating a latch timing signal based on the detection by the differential amplifier, and a latch section for responding to the latch timing signal to latch the complementary signals transferred thereto. A reliable and high-speed signal transmission can be achieved even in a semiconductor device having a large chip size.