Abstract: An inverter and power transmission coils are connected such that currents flow in opposite directions to each other when selection switches of respective power transmission coils adjacent to each other, out of a plurality of power transmission coils disposed in the movement direction of a mobile body, are caused to be conductive. The difference in currents flowing in the opposite directions is measured, and compared with a threshold, whereby whether or not a power reception coil mounted to the mobile body is present above the power transmission coil can be determined.

Abstract: The sulfide solid-state battery of the present disclosure has a battery laminate having one or more unit batteries; and an inorganic coating layer covering at least a portion of the periphery of the battery laminate. The unit battery is formed by laminating a positive electrode layer, a solid electrolyte layer, and a negative electrode layer in this order. At least one of the positive electrode layer, the solid electrolyte layer, and the negative electrode layer contains a sulfide solid electrolyte. The inorganic coating layer is made of an inorganic glass having a glass transition point of 260° C. or higher and 360° C. or lower.

Abstract: An apparatus includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit which is configured to activate first and second internal signals in a time-division manner in response to a first external command A first number of the word lines arc selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal. The second number is smaller than the first number.

Abstract: The resin current collector of the present disclosure includes a base material resin, a conductive resin layer including a conductive filler dispersed in the base material resin, and a fluorine-based resin layer laminated on the conductive resin layer. Further, in the use of the resin current collector in the laminated battery, the current collector of at least one end face of the laminated battery is the resin current collector of the present disclosure, and the conductive resin layer is in contact with the other layer constituting the laminated battery, and the fluorine-based resin layer is disposed so as to face the opposite side to the other layer constituting the laminated battery.

Abstract: An apparatus that includes a memory cell array, an I/O terminal supplied with an original write data in a normal operation, a compression logic circuit configured to generate a compressed test data in a test operation based on a test read data read from the memory cell array, and a syndrome generator configured to generate a first syndrome based on the original write data in the normal operation and generate a second syndrome based on the compressed test data in the test operation.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: A wireless power feeding system includes: a power transmission circuit portion for converting DC power supplied from a main power supply, to AC power, and for supplying the AC power to a power-transmission-side coil; input power control means for controlling the AC power to be supplied to the power-transmission-side coil; a power-reception-side coil which is magnetically coupled with the power-transmission-side coil and to which AC power is transmitted from the power-transmission-side coil through magnetic energy accumulated between the power-reception-side coil and the power-transmission-side coil; a power reception circuit including a rectifier for converting the AC power transmitted to the power-reception-side coil, to DC, and a power-reception-side DC/DC converter; and power reception circuit control means for controlling rectifier output voltage to be a maximum efficiency voltage at which power transmission efficiency becomes maximum.

Abstract: An error correction code (ECC) circuit receives a plurality of data hits and provides a one or more parity bits. The parity bits are used to locate and/or correct errors in the data bits. The ECC circuit splits the plurality of data bits into multiple portions and then processes these portions sequentially to generate preliminary parity bits. Once the portions of the data have been sequentially processed, the preliminary parity bits are combined to generate the parity bits.

Abstract: An inverter and power transmission coils are connected such that currents flow in opposite directions to each other when selection switches of respective power transmission coils adjacent to each other, out of a plurality of power transmission coils disposed in the movement direction of a mobile body, are caused to be conductive. The difference in currents flowing in the opposite directions is measured, and compared with a threshold, whereby whether or not a power reception coil mounted to the mobile body is present above the power transmission coil can be determined.

Abstract: Apparatuses, systems, and methods for error correction for selected bit pairs. A memory device may include an error correction code (ECC) circuit which may receive data bits as part of a read or write operation and generate parity bits based on the data bits. The parity bits may be used to locate and correct errors in the data bits. The parity bits may be generated based on a syndrome value. Each of the individual data bits may be associated with a syndrome value. In addition, some selected pairs of data bits may also be associated. with a syndrome value. This may allow the ECC circuit to correct errors in individual data bits or in one of the selected pairs of data bits. In some embodiments, the selected pairs may represent adjacent memory cells along a word line.

Abstract: Apparatuses, systems, and methods for error correction for selected bit pairs. A memory device may include an error correction code (ECC) circuit which may receive data bits as part of a read or write operation and generate parity bits based on the data bits. The parity bits may be used to locate and correct errors in the data bits. The parity bits may be generated based on a syndrome value. Each of the individual data bits may be associated with a syndrome value. In addition, some selected pairs of data bits may also be associated with a syndrome value. This may allow the ECC circuit to correct errors in individual data bits or in one of the selected pairs of data bits. In some embodiments, the selected pairs may represent adjacent memory cells along a word line.

Abstract: An output terminal of a contact type charger connected to an AC power supply 1 and being for boosting or stepping down an input voltage, and an output terminal of a non-contact type charger for receiving power in a non-contact manner are connected to an input terminal of a DC/DC converter via an integrated bus, a DC link capacitor is connected between an AC/DC converter and an isolated DC/DC converter included in the contact type charger, an integrated capacitor is connected to the integrated bus, and a control circuit adjusts a DC voltage of the DC link capacitor or the integrated capacitor such that at least one of power losses or a total power loss of the contact type charger, the non-contact type charger, and the DC/DC converter is reduced.

Abstract: A power receiving device of a wireless power transfer system receives power from a power transmitting circuit connected to a power source and having a power transmitting coil. The power receiving device includes a power receiving circuit, a power converter, an LC filter, and switches which are controlled by a control device on the basis of voltage detected by voltage detection means for detecting output voltage of the power receiving circuit, so that conduction between the power receiving circuit and the power converter is interrupted during a non-power-transfer period.

Abstract: A first converter performs power conversion and outputs AC power. The AC power outputted from the first converter is supplied to a first coil. The first coil is magnetically coupled with a second coil, and the AC power is transmitted from the first coil to the second coil. A second converter is connected to the second coil, and converts the AC power transmitted to the second coil to DC power and supplies the DC power to a load. A first control unit controls the first converter so as to alternately switch between a first state of outputting rectangular wave voltage which cyclically changes and a second state of outputting constant reference voltage, on the basis of required power of the load.

Abstract: After a free-form surface is machined on an elongated material 1 with a projection 3 and a blade root 4 held, the holding of the projection 3 is released to release strain generated during machining. Upon release of the holding, the entire elongated material 1 deforms, and the projection 3 moves from a holding position A to a strain-released position B. A re-holding position C obtained by correcting the position B by the deformation amount of the elongated material 1 due to the weight of the elongated material 1 is determined, and the projection 3 is held again at the re-holding position C for further machining the free-form surface on the elongated material 1.

Abstract: Apparatuses, systems, and methods for multi-pump error correction. An error correction code (ECC) circuit may receive a plurality of data bits and provide a one or more parity bits. The parity bits may be used to locate and/or correct errors in the data bits. The ECC circuit may split the plurality of data bits into multiple portions and then process these portions sequentially to generate preliminary parity bits. Once the portions of the data have been sequentially processed, the preliminary parity bits may be combined to generate the parity bits.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: Error correction control (ECC) circuits for memory devices and related apparatuses, systems, and methods are disclosed. An apparatus includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared main input/output (MIO) lines. The single set of shared MIO lines are shared by the plurality of memory banks. The apparatus also includes a single ECC control circuit configured to generate corrected read data responsive to the read data received by the ECC control circuit input. The apparatus further includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.

Abstract: Disclosed herein is an apparatus that includes a command shifter configured to receive a command pulse and generate a plurality of first command shifted pulses in parallel, wherein each of the plurality of first command shifted pulses has the same width as the command pulse and the plurality of first command shifted pulses have different phases from each other, and a command filter configured to determine if a plurality of second command shifted pulses are generated correspondingly to the plurality of first command shifted pulses or not generated responsive to pulse overlapping among at least ones of the plurality of first command shifted pulses.

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.