Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-di vision manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

Abstract: After a free-form surface is machined on an elongated material 1 with a projection 3 and a blade root 4 held, the holding of the projection 3 is released to release strain generated during machining. Upon release of the holding, the entire elongated material 1 deforms, and the projection 3 moves from a holding position A to a strain-released position B. A re-holding position C obtained by correcting the position B by the deformation amount of the elongated material 1 due to the weight of the elongated material 1 is determined, and the projection 3 is held again at the re-holding position C for further machining the free-form surface on the elongated material 1.

Abstract: A system for refresh operations in semiconductor memories, and an apparatus and method therefore, are described. The system includes, for example, memory cells in memory banks that are refreshed during a self-refresh operation or an auto refresh operation. The self-refresh operation includes a different number of refresh activations than the auto refresh operation. The system further includes a row control circuit configured to refresh the memory cells in the memory banks based on refresh control signals received from a refresh control circuit, the refresh control signals provided by the refresh control circuit based on internal control signals received by the refresh control circuit from a command control circuit. The auto refresh operation includes a per bank refresh operation configured to refresh a corresponding memory bank or an all-bank refresh operation configured to refresh all memory banks.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating a refresh address locally at a memory bank. The memory bank may include or be associated with a bank logic circuit that latches an initial refresh address from a global row address bus for a first pump of a refresh operation. The bank logic circuit then updates the latched refresh address received to generate a new refresh address for a second pump of the refresh operation. A memory device may include multiple memory banks that share the global row address bus.

Abstract: A system for refresh operations including multiple refresh activations, and a method and an apparatus therefore, are described. The system includes, for example, a memory array; a command address input circuit configured to provide a command for a per bank refresh operation or an all-bank refresh operation, a command control circuit configured to receive the command, and provide first and second internal control signals; a refresh control circuit configured to provide a first refresh control signal; and a row control circuit configured to provide a second refresh control signal. The provided first internal control signal is based on the provided command. For the per bank refresh operation, the provided second internal control signal is based on the second refresh control signal, and, for the all-bank refresh operation, the provided second internal control signal is based on the first internal control signal delayed by the command control circuit.

Abstract: A memory array having a main memory array and a redundant memory array. The redundant memory array includes redundant memory arranged in replacement units to which memory of the main memory are mapped. Each replacement unit includes columns of redundant memory arranged in input-output (IO) groups and further includes columns of redundant memory from a plurality of IO groups. The IO groups have columns of memory associated with a plurality of different IOs and the plurality of IO groups of the replacement unit adjacent one another.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: There is provided a novel optical sensor utilizing a surface plasmon resonance technique which is capable of detecting a substance to be detected with high sensitivity independently of a wavelength of irradiated light and is capable of obtaining information, other than a refraction index, on the substance to be detected. At the center of a surface of a metallic film 2 which is formed on a substrate and has no aperture, a circular depression 4 with a diameter of 0.1 to 250 nm is formed and with the depression 4 defined as a center, a plurality of depressions 3 are concentrically formed at intervals of 450 to 530 nm.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further embodiments provide for mapping non-redundant rows associated with a section associated with a block failure to distributed redundant rows.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of the present invention comprises a DRF bus, a DR11F bus, a GDRF bus and a GDR11F bus. The DRF bus and DR11F bus, and the GDRF bus and GDR11F bus, are placed in parallel for the purpose of reducing the number of times toggle operations of a data bus are performed at the time of a data transmission. The DR11F bus is added to make the DRF11F bus perform a toggle operation only when the DRF buses on both sides are made to perform a toggle operation if the data transmission were performed in a conventional system.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode.

Abstract: In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of the present invention comprises a DRF bus, a DR11F bus, a GDRF bus and a GDR11F bus. The DRF bus and DR11F bus, and the GDRF bus and GDR11F bus, are placed in parallel for the purpose of reducing the number of times toggle operations of a data bus are performed at the time of a data transmission. The DR11F bus is added to make the DRF11F bus perform a toggle operation only when the DRF buses on both sides are made to perform a toggle operation if the data transmission were performed in a conventional system.

Abstract: Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address to an internal row address, wherein the internal row address comprises a section address, determining whether a section corresponding to the section address includes an error, and if the section includes an error, converting the internal row address to a redundant row address, wherein mapping the external row address to the internal row address is initiated prior to determining whether the section replacement should be performed. Further embodiments include a method for receiving a row address for a row in a memory section including a non-2^n number of normal rows and mapping the row address to a redundant row address by subtracting a value from the row address.

Abstract: In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of the present invention comprises a DRF bus, a DR11F bus, a GDRF bus and a GDR11F bus. The DRF bus and DR11F bus, and the GDRF bus and GDR11F bus, are placed in parallel for the purpose of reducing the number of times toggle operations of a data bus are performed at the time of a data transmission. The DR11F bus is added to make the DRF11F bus perform a toggle operation only when the DRF buses on both sides are made to perform a toggle operation if the data transmission were performed in a conventional system.

Abstract: Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further embodiments provide for mapping non-redundant rows associated with a section associated with a block failure to distributed redundant rows.

Abstract: Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode.