Abstract: Such a device is disclosed that includes an internal voltage generating circuit generating an internal voltage by lowering an external potential and supplying the generated internal voltage to a power supply line, a switch being connected between a grounding wire to which a ground voltage is supplied and the power supply line, and a one-shot signal generating unit controlling turning on and off of the switch, wherein the one-shot signal generating unit brings the switch into conduction synchronously with start of generating the internal voltage by the internal voltage generating circuit.

Abstract: Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal.

Abstract: A semiconductor device is provided with a clock output control circuit which supplies a long-period clock signal having a period longer than an internal clock signal within an active period and supplies the internal clock signal within a read period subsequent to the active period, a clock transfer circuit which transfers the internal clock signal and the long-period clock signal outputted from the clock output control circuit, a data input/output terminal, and an input/output circuit which outputs read data to the data input/output terminal in synchronization with the internal clock signal having been transferred by the clock transfer circuit.

Abstract: Such a device is disclosed that includes a terminal, a first voltage generator generating, when activated, a voltage at the terminal and stopping, when deactivated, generating the voltage, and a second voltage generator generating, when activated, the voltage at the terminal and stopping, when deactivated, generating the voltage. The first voltage generator being configured to be activated in response to a first control signal taking an active level and deactivated in response to the first control signal taking an inactive level, and the second voltage generator being configured to be activated in response to each of the first control signal and a second control signal taking an active level and deactivated in response to at least one of the first and second control signal taking an inactive level.

Abstract: To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first, second, and third buffers to the second bus line; fifth to eighth banks connected via the fourth and fifth buffers to the second bus line; and a data input/output unit connected to the second bus line. Transfer delay times of the fourth and fifth buffers are longer than transfer delay times of the first, second, and third buffers. Thereby, it becomes possible to eliminate differences in data transfer times resulting from differences in distances between far and near ends without causing significant increase in wire density, increase in power consumption, or the like.

Abstract: The semiconductor device includes a first pair of data lines, a second pair of data lines, a third pair of data lines, a first amplifier (SA) connected to the first pair of data lines, a first switch that controls connection between the first pair of data lines and the second pair of data lines, a second switch that controls connection between the second pair of data lines and the third pair of data lines, a second amplifier that amplifies data on the second pair of data lines, for output to the third pair of data lines, a third amplifier connected to the third pair of data lines, and a control circuit that controls the second switch forming a pair of switches. When two data lines constituting the third pair of data lines both assume a first state, the control circuit controls the second switch to be turned off, thereby controlling the second pair of data lines and the third pair of data lines to be disconnected.

Abstract: To provide a semiconductor device including: first and second bus lines; a first buffer connected between the first and second bus lines; second and third buffers connected to the first bus line; fourth and fifth buffers connected to the second bus line; first to fourth banks connected via the first, second, and third buffers to the second bus line; fifth to eighth banks connected via the fourth and fifth buffers to the second bus line; and a data input/output unit connected to the second bus line. Transfer delay times of the fourth and fifth buffers are longer than transfer delay times of the first, second, and third buffers. Thereby, it becomes possible to eliminate differences in data transfer times resulting from differences in distances between far and near ends without causing significant increase in wire density, increase in power consumption, or the like.

Abstract: A semiconductor device in which a plurality of devices provided with mutually identical functions are stacked includes: a chip selection terminal by which the semiconductor device selects devices, a prescribed terminal for generating a second internal signal that is selectively switched from a first internal signal from the chip selection terminal, and an input-switching circuit for selectively switching the first internal signal and the second internal signal.

Abstract: When a redundancy circuit is fully used and a further defect is present, an irreparable-state signal is produced. When the irreparable-state signal is produced, a defect is judged. When the irreparable-state signal is not produced, upon testing for quality judgment, extraction of a defective memory cell, programming an address of the defective memory cell into a fuse, and confirmation about whether or not the address is properly programmed are carried out. Quality judgment is possible only by confirming address information of the written address as confirmation after programming into the electric fuse.

Abstract: When a redundancy circuit is fully used and a further defect is present, an irreparable-state signal is produced. When the irreparable-state signal is produced, a defect is judged. When the irreparable-state signal is not produced, upon testing for quality judgment, extraction of a defective memory cell, programming an address of the defective memory cell into a fuse, and confirmation about whether or not the address is properly programmed are carried out. Quality judgment is possible only by confirming address information of the written address as confirmation after programming into the electric fuse.