Patents by Inventor TAL KUZI
TAL KUZI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10365707Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.Type: GrantFiled: December 9, 2016Date of Patent: July 30, 2019Assignee: INTEL CORPORATIONInventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
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Publication number: 20190011976Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 13, 2018Publication date: January 10, 2019Applicant: Intel CorporationInventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S. R. Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
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Patent number: 10114448Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.Type: GrantFiled: July 2, 2014Date of Patent: October 30, 2018Assignee: Intel CorporationInventors: Jawad Haj-Yihia, Eliezer Weissmann, Vijay S R Degalahal, Nadav Shulman, Tal Kuzi, Itay Franko, Amit Gur, Efraim Rotem
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Publication number: 20180164870Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.Type: ApplicationFiled: December 8, 2016Publication date: June 14, 2018Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
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Publication number: 20180164873Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.Type: ApplicationFiled: December 9, 2016Publication date: June 14, 2018Inventors: Alexander Gendler, Doron Rajwan, Tal Kuzi, Dean Mulla, Ariel Szapiro, Nir Tell
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Patent number: 9864667Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 25, 2015Date of Patent: January 9, 2018Assignee: Intel CorporationInventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
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Publication number: 20170285703Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.Type: ApplicationFiled: June 15, 2017Publication date: October 5, 2017Inventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
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Patent number: 9710054Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.Type: GrantFiled: February 28, 2015Date of Patent: July 18, 2017Assignee: Intel CorporationInventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
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Publication number: 20170177065Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.Type: ApplicationFiled: December 16, 2015Publication date: June 22, 2017Inventors: Doron Rajwan, Dorit Shapira, Itai Feit, Nadav Shulman, Efraim (Efi) Rotem, Tal Kuzi, Eliezer Weissmann, Tomer Ziv, Nir Rosenzweig
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Publication number: 20170090945Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Applicant: Intel CorporationInventors: Doron Rajwan, Eliezer Weissmann, Yoni Aizik, Itai Feit, Tal Kuzi, Tomer Ziv, Nadav Shulman
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Patent number: 9541949Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.Type: GrantFiled: September 22, 2014Date of Patent: January 10, 2017Assignee: Intel CorporationInventors: Tal Kuzi, Nadav Shulman, Ofer J. Nathan, Ori Levy, Itai Feit
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Publication number: 20160252952Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.Type: ApplicationFiled: February 28, 2015Publication date: September 1, 2016Inventors: Israel Diamand, Asaf Rubinstein, Arik Gihon, Tal Kuzi, Tomer Ziv, Nadav Shulman
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Publication number: 20160085263Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.Type: ApplicationFiled: September 22, 2014Publication date: March 24, 2016Inventors: TAL KUZI, NADAV SHULMAN, OFER J. NATHAN, ORI LEVY, ITAI FEIT
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Publication number: 20160004296Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Applicant: Intel CorporationInventors: JAWADH HAJ-YIHIA, ELIEZER WEISSMANN, VIJAY S R DEGALAHAL, NADAV SHULMAN, TAL KUZI, ITAY FRANKO, AMIT GUR, EFRAIM ROTEM