Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system may receive data units from a host device. A first controller of the memory system may generate a protocol unit using the data units. A second controller of the memory system may generate a data storage unit using data from the protocol unit, and may store the data unit to a memory device. The memory system may perform error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system may, for a write operation, re-request data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.

Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system receives data units from a host device. A first controller of the memory system generates a protocol unit using the data units. A second controller of the memory system generates a data storage unit using data from the protocol unit, and stores the data unit to a memory device. The memory system performs error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system, for a write operation, re-requests data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.

Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.

Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

Abstract: Methods, systems, and devices for power management associated with memory and a controller are described. A memory system performs a power management operation that accounts for power usage by any combination of application specific integrated circuits (ASICs) and memory arrays. The power management operation includes multiple logical unit numbers (LUNs) assigned to a single ASIC, which increases a quantity of bits for communicating a power usage. An ASIC included in a memory system may utilize twice as many bits for communicating power usage information when compared to a NAND array. As part of the power management operation, an ASIC may transmit, to a controller, a first set of bits indicating a power usage of the ASIC, a first subset of the set of bits transmitted during a first instance of a token ring and a second subset of the set of bits transmitted during a second instance of the token ring.

Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.

Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.

Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

Abstract: A memory device includes a set of memory dies, each memory die of the set of memory dies including a memory array and first control logic operatively coupled to the memory array, and an application-specific integrated circuit (ASIC) including a general-purpose input/output component (GPIO) including at least one digital pad communicably coupled to each memory die of the set of memory dies, and second control logic, operatively coupled to memory, to perform operations related to peak power management (PPM).

Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system may receive data units from a host device. A first controller of the memory system may generate a protocol unit using the data units. A second controller of the memory system may generate a data storage unit using data from the protocol unit, and may store the data unit to a memory device. The memory system may perform error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system may, for a write operation, re-request data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.

Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

Abstract: Methods, systems, and devices for error protection for managed memory devices are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.

Abstract: Methods, systems, and devices for data recovery using ordered data requests are described. In some examples, a memory system may receive data units from a host device. A first controller of the memory system may generate a protocol unit using the data units. A second controller of the memory system may generate a data storage unit using data from the protocol unit, and may store the data unit to a memory device. The memory system may perform error detection operations using respective sets of parity bits for each of the units. Upon detecting an error, the memory system may, for a write operation, re-request data associated with error and regenerate the units to correct for the error, or, for a read operation, re-read data associated with the error and regenerate the units to correct for the error.

Abstract: Methods, systems, and devices for error notification using an external channel are described. In some cases, a memory system having a host-driven logical block interface may issue a notification of a detected error using an out of band channel. For example, after receiving a data unit from a host system but prior to storing the data in a memory array of the memory system, the memory system may transmit an acknowledgment to host system to indicate that the data was successfully received. As part of storing the data, the memory system may transfer the data along data paths between various components and perform parity checks at each component. If the memory system detects an error along a data path, the memory system may issue a notification of the error to the host system over the out of band channel.

Abstract: A method and apparatus configured to reduce power consumption of a physical (PHY) interface of a digital memory device. In some configurations, the PHY interface is configured to modulate electrical characteristics of a transmitter and/or receiver on the PHY interface according to an idle state of one or more of the digital memory device or a host computing system.