Patents by Inventor Tamaki Wada
Tamaki Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150118196Abstract: A mammalian cell suspension prevents pulmonary embolism formation during administration of mammalian cells, such as mammalian stem cells, through a blood vessel, and a preventive agent against pulmonary embolism formation during administration of mammalian cells through a blood vessel. suspending mammalian cells, such as mammalian stem cells, are suspended in a physiological aqueous solution containing trehalose or its derivative, or a salt thereof as an active ingredient to prepare a mammalian cell suspension for preventing pulmonary embolism formation during administration of the mammalian cells through a blood vessel, including the mammalian cells and trehalose or its derivative, or a salt thereof as active ingredients. Examples of the mammalian cells can include pancreatic islet cells, dendritic cells, natural killer cells, alpha/beta T cells, gamma/delta T cells, and cytotoxic T lymphocytes in addition to mammalian stem cells.Type: ApplicationFiled: May 2, 2013Publication date: April 30, 2015Applicant: OTSUKA PHARMACEUTICAL FACTORY, INC.Inventors: Tamaki Wada, Masako Doi, Takeshi Kikuchi, Eiji Kobayashi
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Patent number: 9006036Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.Type: GrantFiled: September 18, 2013Date of Patent: April 14, 2015Assignee: Renesas Electronics CorporationInventors: Tomoko Higashino, Yuichi Morinaga, Kazuya Tsuboi, Tamaki Wada
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Publication number: 20140353822Abstract: Reliability of a semiconductor device is improved. A semiconductor device has a base material comprised of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. Further, the semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor means is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member such as the wire.Type: ApplicationFiled: May 15, 2014Publication date: December 4, 2014Applicant: Renesas Electronics CorporationInventors: Kenji OYACHI, Tamaki WADA, Yuichi MORINAGA
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Publication number: 20140093961Abstract: Methods of washing adherent cells, capable of effectively suppressing cell death due to proteolytic enzyme treatment for detaching the adherent cell from a culture vessel and subsequent cell treatment; cell-washing solutions used for the washing method; methods of producing cell suspensions for transplantation using the cell-washing solution; and kits comprising the cell-washing solution. Trehalose or its derivative or a salt thereof is added to physiological aqueous solutions to prepare cell-washing solutions containing trehalose or its derivative or a salt thereof as an active ingredient. The cell-washing solutions can be used to wash adherent cells before detaching the adherent cells from a culture vessel by proteolytic enzyme treatment to suppress cell death due to the proteolytic enzyme treatment. The concentration of trehalose applied to the cell-washing solution may be a concentration capable of suppressing the cell death due to the proteolytic enzyme treatment, such as 0.1 to 20 (w/v)%.Type: ApplicationFiled: September 24, 2013Publication date: April 3, 2014Applicant: OTSUKA PHARMACEUTICAL FACTORY, INC.Inventors: Eiji KOBAYASHI, Tamaki WADA, Masako DOI
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Publication number: 20140080260Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.Type: ApplicationFiled: September 18, 2013Publication date: March 20, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tomoko HIGASHINO, Yuichi MORINAGA, Kazuya TSUBOI, Tamaki WADA
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Patent number: 8587135Abstract: A semiconductor device has a conductive member coupled to the surface of a bonding pad exposed from an opening formed in a passivation film. A second planar distance between a first end of an electrode layer and a first end of a bonding pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the bonding pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the bonding pad.Type: GrantFiled: November 21, 2012Date of Patent: November 19, 2013Assignee: Renesas Electronics CorporationInventors: Tamaki Wada, Akihiro Tobita, Seiichi Ichihara
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Publication number: 20130260461Abstract: The present invention provides a mammalian stem cell suspension containing mammalian stem cells and at least one polysaccharide such as trehalose, and the like; a mammalian stem cell aggregation inhibitor containing polysaccharide such as trehalose, and the like; a method of suppressing aggregation of mammalian stem cells, containing suspending the mammalian stem cells in an aqueous physiological solution containing polysaccharide; an inhibitor of a decrease in the survival rate of mammalian stem cells containing polysaccharide such as trehalose and the like; a method of suppressing a decrease in the survival rate of mammalian stem cells, containing suspending the mammalian stem cells in an aqueous physiological solution containing polysaccharides, and the like.Type: ApplicationFiled: November 9, 2011Publication date: October 3, 2013Applicants: JICHI MEDICAL UNIVERSITY, OTSUKA PHARMACEUTICAL FACTORY, INC.Inventors: Eiji Kobayashi, Tamaki Wada, Yasutaka Fujita, Norihiro Yoshinaga, Masako Doi, Yasuhiro Fujimoto, Takumi Teratani
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Patent number: 8530278Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.Type: GrantFiled: July 8, 2011Date of Patent: September 10, 2013Assignee: Renesas Electronics CorporationInventors: Nobuyasu Muto, Naoki Kawanabe, Hiroshi Ono, Tamaki Wada
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Patent number: 8338288Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.Type: GrantFiled: April 6, 2011Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Tamaki Wada, Akihiro Tobita, Seiichi Ichihara
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Publication number: 20110269268Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.Type: ApplicationFiled: July 8, 2011Publication date: November 3, 2011Inventors: NOBUYASU MUTO, Naoki Kawanabe, Hiroshi Ono, Tamaki Wada
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Publication number: 20110248406Abstract: In connection with a semiconductor device in which a conductive member is coupled to the surface of a bonding pad exposed from an opening formed in a passivation film, there is provided a technique able to suppress the occurrence of a crack in the passivation film. A second planar distance between a first end of an electrode layer and a first end of a pad is greater than a first planar distance between the first end of the electrode layer and a first end of an opening. Since the second planar distance between the first end of the electrode layer and the first end of the pad is long, even when a coupled position of wire is deviated to the first end side of the electrode layer, stress caused by coupling of the wire to a stepped portion of the electrode layer can be prevented from being transmitted to the first end portion of the pad.Type: ApplicationFiled: April 6, 2011Publication date: October 13, 2011Applicant: Renesas Electronics CorporationInventors: Tamaki WADA, Akihiro TOBITA, Seiichi ICHIHARA
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Publication number: 20110227234Abstract: A multifunction card device has an external connection terminal, an interface controller, a memory, and the security controller connected to the interface controller and the external connection terminal. The interface controller has a plurality of interface control modes, and controls an external-interface action and a memory interface action by the control mode according to the instruction from the outside. The external connection terminals have an individual terminal individualized for every interface control mode, and a communalized common terminal. A clock input terminal, a power supply terminal, and an earthing terminal are included in the common terminals. A data terminal, and a dedicated terminal of the security controller are included in the individual terminals. Partial communalization and individualization of an external connection terminal attain a guarantee of the reliability of an interface, and increase control of physical magnitude to some kinds of interface control modes.Type: ApplicationFiled: June 3, 2011Publication date: September 22, 2011Inventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
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Patent number: 7981788Abstract: The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. Since it becomes possible to form the wire of two directions on the pad of a memory chip by performing the over-bonding of reverse bonding by ball bonding, an effect equivalent to continuation stitch bonding of wedge bonding can be produced by ball bonding. Hereby, the degree of freedom of a chip layout and the degree of freedom of the lead layout of substrate 3 can be improved, and the packaging density on a substrate in a chip lamination type semiconductor device (memory card) can be improved.Type: GrantFiled: July 10, 2006Date of Patent: July 19, 2011Assignee: Renesas Electronics CorporationInventors: Nobuyasu Muto, Naoki Kawanabe, Hiroshi Ono, Tamaki Wada
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Patent number: 7971793Abstract: The present invention provides a memory card equipped with an interface controller connected to external connecting terminals, a memory connected to the interface controller, and a security controller connected to the interface controller. A second external connecting terminal capable of supplying an operating power supply to the security controller is provided aside from a first external connecting terminal which supplies an operating power supply to the interface controller and the memory. An interface unit of the interface controller connected to the security controller receives the operating power supply from the second external connecting terminal and thereby enables a stop of the supply of the operating power supply from the first external connecting terminal. Even if the supply of the operating power supply to the interface controller is cut off, the output of the interface unit is not brought to an indefinite state.Type: GrantFiled: November 27, 2007Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Tamaki Wada, Michiaki Sugiyama, Junichiro Osako
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Patent number: 7971791Abstract: A multifunction card device has an external connection terminal, an interface controller, a memory, and the security controller connected to the interface controller and the external connection terminal. The interface controller has a plurality of interface control modes, and controls an external-interface action and a memory interface action by the control mode according to the instruction from the outside. The external connection terminals have an individual terminal individualized for every interface control mode, and a communalized common terminal. A clock input terminal, a power supply terminal, and an earthing terminal are included in the common terminals. A data terminal, and a dedicated terminal of the security controller are included in the individual terminals. Partial communalization and individualization of an external connection terminal attain a guarantee of the reliability of an interface, and increase control of physical magnitude to some kinds of interface control modes.Type: GrantFiled: July 3, 2003Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
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Patent number: 7946500Abstract: An antenna connection function for a noncontact interface is provided by suppressing a modification in a pin arrangement and a pin shape of a memory card that does not correspond to the noncontact interface. Two antenna connecting pins having the memory card are divided into two areas in which a size of one potential supply pin is the largest and used as a split pin arranged at intervals. Because a size of the two antenna connecting pins is at maximum as large as the size of the potential supply pin, the two antenna connecting pins are provided and the memory card that corresponds to the noncontact interface is obtained by devoting a pin area having the size of the one potential supply pin to the memory card that does not correspond to the noncontact interface. Accordingly, the pin area of the memory card that corresponds to the noncontact interface can be formed without departing from the pin area of the memory card that does not correspond to the noncontact interface.Type: GrantFiled: December 16, 2007Date of Patent: May 24, 2011Assignee: Renesas Electronics CorporationInventors: Hirotaka Nishizawa, Akira Higuchi, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama
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Publication number: 20100267419Abstract: In an IC card, there is provided a technique capable of large expandability of a memory volume, and a memory volume and a cost matched with a user's requirement. A SIM adapter 101 has a top panel 104 for covering a recess portion. In the top panel 104, when a memory card 103 is not inserted, the top panel 104 is positioned at a first height, and, when the memory card 103 is inserted, a part of the top panel 104 is engaged with a part of the SIM adapter 101 so that the top panel is latched at a second height higher than the first height. Also, into a SIM adapter, a top panel for fixing a memory card when the memory card is inserted is inserted, and a part of the top panel is engaged with a part of the SIM adapter so that the top panel is latched when the memory card is inserted.Type: ApplicationFiled: December 10, 2007Publication date: October 21, 2010Inventors: Hirotaka Nishizawa, Hironori Iwasaki, Hideo Koike, Junichiro Osako, Tamaki Wada, Takashi Totsuka
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Publication number: 20100257313Abstract: A semiconductor device has operation modes selectable through the control by a second microcomputer (113). In a first mode, an operation of a memory controller (105) responding to a memory card command from a memory card interface terminal and an operation of a first microcomputer (106) responding to an IC card command from an IC card interface terminal are separately performed. In a second mode, the first microcomputer operates in response to the IC card command from the IC card interface terminal. In a third mode, the memory controller and the first microcomputer operate in response to an undefined IC card command from the IC card interface terminal. In a fourth mode, the memory controller and the first microcomputer operate in response to the memory card command from the memory card interface terminal. Convenience of the semiconductor device having an IC card function and a memory card function is improved.Type: ApplicationFiled: May 16, 2007Publication date: October 7, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hirotaka Nishizawa, Junichiro Osako, Minoru Shinohara, Tamaki Wada, Kunihirio Katayama, Shigemasa Shiota
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Publication number: 20100072284Abstract: Connector terminals are arranged at the center of a thin memory card 1802, thereby preventing an electrical short circuit between the terminals. A step is provided to the thin memory card 1802, thereby allowing the IC chips to be stacked in a thick portion. Adhesion portions of the connector terminals 3303 are located at a position on a card insertion port side of a substrate 3002, thereby preventing the destruction of the connector terminals at the time of the card insertion. An upper retainer lid 3003 is provided on an upper portion of the connector terminals 3303, thereby preventing the deflection of the card.Type: ApplicationFiled: December 12, 2007Publication date: March 25, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hirotaka NISHIZAWA, Hideo KOIKE, Hironori IWASAKI, Junichiro OSAKO, Minoru SHINOHARA, Tamaki WADA, Takashi TOTSUKA
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Patent number: 7669773Abstract: To realize compatibility with an SIM card and adaptation to a high-speed memory access in an IC card module having a microcomputer and a memory card controller. An IC card module includes a plurality of first external connecting terminals and a plurality of second external connecting terminals both exposed to one surface of a card substrate, a microcomputer connected to the first external connecting terminals, a memory controller connected to the second external connecting terminals, and a volatile memory connected to the memory controller. The shape of the card substrate and the layout of the first external connecting terminals are based on a standard of plug-in UICC of ETSI TS 102 221 V4.4.0 (2001-10) or have compatibility. The second external connecting terminals are disposed outside the minimum range of the terminal layout based on the standard for the first external connecting terminals.Type: GrantFiled: October 18, 2007Date of Patent: March 2, 2010Assignee: Renesas Technology Corp.Inventors: Hirotaka Nishizawa, Takashi Totsuka, Kenji Osawa, Junichiro Osako, Tamaki Wada, Michiaki Sugiyama