Abstract: The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance.

Abstract: The present invention relates generally to integrated circuits and more particularly, to a structure and method of forming a hybrid circuit including a tunnel field-effect transistor (TFET) and a conventional field effect transistor (FET). Embodiments of the present invention include a hybrid amplifier which features a TFET common-source feeding a common-gate conventional FET (e.g. a MOSFET). A TFET gate may be electrically isolated from an output from a conventional FET. Thus, a high impedance input may be received by a TFET with a high-isolation output (i.e. low capacitance) at a conventional FET. A hybrid circuit amplifier including a TFET and a conventional FET may have a very high input impedance and a low miller capacitance.

Abstract: Disclosed are a system, a method and a computer program product for accurately modeling the performance of a body-contacted, asymmetric double gate, dynamically depleted (DD), semiconductor-on-insulator (SOI) field effect transistor (FET). This modeling can be performed, using iterative processing, to determine the conditions (e.g., back gate bias voltage, front gate bias voltage, body resistance and body charge) under which the FET channel region transitions from being in a partially depleted (PD) state such that the FET functions as a PD SOI FET to being in a fully depleted (FD) state such that the FET functions as a FD SOI FET. Once these conditions are known (i.e., once the model is generated), the DD SOI FET can be incorporated into top-level integrated circuit designs with specifications that either meet the conditions or do not meet the conditions, depending upon the desired function of the DD SOI FET within the integrated circuit.

Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).