Abstract: There are provided a communications system between a vehicle, a home and a center, a vehicle information communicating apparatus and an indoor information processing apparatus which imposes no limitation on communicating time enables bulk communication. The communications system comprises an on-board server and DSRC on-board equipment which are installed on the vehicle 10 and includes a DSRC base station 23 residing outside the vehicle which can communicate with the DSRC on-board equipment and a PC or a home server 22 residing indoors which is connected to the DSRC base station 23, the communication system having a detection apparatus installed on the vehicle and/or an indoor detection apparatus for detecting the state of the vehicle 10 and a communication activating apparatus for activating the communication of information between the on-board server and the PC or the home server 22 using the detection result of either or both of the detection apparatus.

Abstract: There are provided a communications system between a vehicle, a home and a center, a vehicle information communicating apparatus and an indoor information processing apparatus which imposes no limitation on communicating time enables bulk communication. The communications system comprises an on-board server and DSRC on-board equipment which are installed on the vehicle 10 and includes a DSRC base station 23 residing outside the vehicle which can communicate with the DSRC on-board equipment and a PC or a home server 22 residing indoors which is connected to the DSRC base station 23, the communication system having a detection means installed on the vehicle and/or an indoor detection means for detecting the state of the vehicle 10 and a communication activating means for activating the communication of information between the on-board server and the PC or the home server 22 using the detection result of either or both of the detection means.

Abstract: An apparatus function change service system for changing a function of an apparatus including a reconfigurable chip includes a request receiving section for receiving a request for a function change of the apparatus from a user of the apparatus; a specifying section for specifying a change to be made in the reconfigurable chip for fulfilling the request based on the request; and a changing section for performing the change in the reconfigurable chip based on the specified change to be made in the reconfigurable chip.

Abstract: According to the signal processing method of the invention, control data is previously generated by using the name of a control signal included in an object signal, and then, the object signal including the control signal is input. The name of the control signal in the control data is substituted with the content of the control signal included in the object signal, and then the object signal is processed by a signal processing unit by using the control data including the content of the control signal. Therefore, the signal processing unit can change the processing to be performed on the object signal in accordance with the content of the control signal included in the object signal.

Abstract: In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.

Abstract: An improved LSI design automation system includes: an input unit, a circuit component storage unit, a circuit component selection unit, a design method decision unit, a design process unit, and a component entry unit. The input unit receives LSI function and performance information as a requirements specification and LSI component configuration information. The circuit component storage unit collectively stores a circuit data item, design method information items, and performance information items, as a circuit component. The circuit component selection unit selects a circuit component from the circuit component storage unit for implementation of a desired circuit. The design method decision unit selects an optimum design method information item from the design method information items held by each circuit component. The design process unit generates, modifies, and evaluates a circuit.

Abstract: A plurality of processing elements are connected in cascade so as to constitute a single signal processing apparatus. The signal processing apparatus has a first path for transferring an input data signal and a second path for transferring a processing result of the input data signal.

Abstract: A plurality of signal processing elements are cascade-connected to form a signal processor having three signal paths. The signal processor is a small-sized device which can be shared by sum-of-products calculation and division. In each signal processing element, first and second shifters and an adder-subtracter are used for performing shift addition for multiplication of a variable by a constant which is a basis of the sum-of-products calculation. The adder-subtracter and a third shifter for shifting a result obtained by the adder-subtracter are used for performing subtraction and shifting for obtaining a partial quotient and a partial remainder of division. The partial quotient thus obtained is transferred to the signal processing element in the next stage through a flag holding circuit.

Abstract: In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected.

Abstract: To achieve an LSI automated design satisfying a required function and a required performance with the reuse of existing design data, there are disposed: library element memory means for storing, in the form of elements, existing design data (circuit data) together with design procedures (conversion information) thereof; element arrangement entering means for entering an element arrangement for achieving the desired function; library element specializing means for determining the functions of general-purpose elements; element synthesizing means for synthesizing an element having one function in which the functions of the elements are combined with one another; design data memory means for storing a variety of data; conversion instruction entering means for entering a design target level; conversion method selecting means for selecting a method of converting the elements to the target level, based on information relating to the design procedure of each of the elements; and design data converting means for execu

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

Abstract: In order to establish connections of plural arithmetic units capable of performing basic functions such as filtering in various connection ways, a bus switch is provided which has a plurality of input data lines connected with output terminals of the arithmetic units, at least one external input data line, a plurality of output data lines connected with input terminals of the arithmetic units, and at least one external output data line. In addition, two register sets are provided which hold arithmetic control information designating contents of processes to be performed by the arithmetic units and connection control information designating connection ways within the bus switch. Depending on the broadcasting system, information held by one of the register sets and information held by the other are updated, and, according to a process algorithm, either one of the two register sets is selected.

Abstract: An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell is specified by a denotation of E?(column number),y(row number)! where the column number x is 1.ltoreq.x.ltoreq.4 and the row number y is x.ltoreq.y.ltoreq.4. Each arithmetic cell has a multiplier and an adder for multiply-add operation. An arithmetic cell, specified by E?x,y! where 2.ltoreq.x.ltoreq.4 and x.ltoreq.y.ltoreq.4, receives data from an E?x-1,y! arithmetic cell via a direct bus as well as from an E?x-1,y-1! arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.

Abstract: In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.

Abstract: In a data processor such as a CAD system for LSI design, a hierarchical structure of a plurality of objects each having a circuit data is represented in a relation between a window on a menu screen and a plurality of figure blocks on the window. One of the plural figure blocks on the window is represented in a different window so as to represent a multi-hierarchical structure of the objects, and a block figure group is arranged on the different window. A user selects, using a mouse, an object to be processed on a menu screen representing a floor plan.

Abstract: With respect to each bit of a multiplier factor, it is judged whether or not the multiplier factor is a variable or a constant. If the multiplier factor is a constant, it is judged whether or not a bit of concern in the multiplier factor has the value of 1. Only if the bit of concern in the multiplier factor is 1, there is generated a circuit for outputting, as a partial product, a signal indicating a multiplicand. The signal indicating the multiplicand is then shifted by one bit so that the resulting signal is newly set as the signal indicating the multiplicand. By repeatedly executing the foregoing process with respect to all the bits of the multiplier factor, a circuit for calculating a partial product with respect to each bit of the multiplier factor is generated.

Abstract: This invention discloses an improved signal processor comprising first to third arithmetic units forming a pipeline structure, first to third control information hold circuits each of which holds control information for its corresponding arithmetic unit, first to third selection circuits, and first to third signal transfer circuits. Transfer of a selection signal is delayed by a proportional interval of time to the processing time of each arithmetic unit. In order to perform the switching of arithmetical operations in each arithmetic unit according to the data flow in the pipeline processing, each selection circuit selects among the control information hold circuits depending on the selection signal transferred and provides control information held in a selected control information hold circuit to a corresponding arithmetic unit.

Abstract: A logic synthesis unit generates configuration data of a virtual logic circuit composed of virtual elements, or logic gates each of which carries only a functional definition, in order to realize a logic circuit functional description fed through an input unit. A logic transformation unit, referring to a standard cell library, performs the allocation of real elements for implementation to respective virtual elements to transform the virtual logic circuit into a real logic circuit having the same function as the virtual logic circuit. Then the logic transformation unit, referring to a timing analysis unit, selects a particular real element with a smallest driving capacity from among the real elements in the library performing the same function as an object virtual element and satisfying both fan-out restrictions and delay constraints, and allocates the real element thus selected to the virtual element.

Abstract: A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.