Abstract: Disclosed is here units or processing steps respectively for detecting loops in a logic circuit to determine logic levels associated with first coordinates of respective elements such that a location where the overlapping of the loops develop the maximum value is assigned as a feedback routing, for determining positional relationships between elements at the reference level to relieve congestion of routings in the vicinity of the reference level, for sequentially achieving the maximum matching on a bipartite graph constituted with connective relationships of the elements for each level beginning from the reference level to determine positional relationships related to second coordinates so as to assign elements associated with each other to the same position, and for defining virtual routing length to achieve routing in accordance with a result of sorting by use of the virtual routing lengths.

Abstract: In the case where a multiplier factor is a constant, if the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is larger than the number of the bits having the value of 0, a circuit for performing multiplication by using the logic NOT number of the multiplier factor, which is obtained by inverting all the bits in the multiplier factor by the logic NOT operation is generated. If the number of the bits having the value of 1 in the multiplier factor is 3 or more and if it is smaller than the number of the bits having the value of 0, the multiplier factor is divided so that an adder for adding partial products forms a well-balanced binary tree. Conversely, if the number of the bits having the value of 1 in the multiplier factor is 2 or less, an add shift multiplier for calculating partial products only with respect to the bits having the value of 1 is generated.

Abstract: Together with circuit data of circuit elements, there is stored, in a memory device, external specification information of each of the circuit elements, the information including (i) function information of each of the terminals of the circuit elements and (ii) selection information representing a wiring condition for each of the terminals. When the element arrangement and external specification information of a circuit to be designed, are entered, pieces of external specification information are compared with one another to obtain pairs of wiring candidates of a circuit which connects, to one another, the circuit elements of the circuit to be designed. Based on the pairs of wiring candidates, there is generated wiring information which satisfies each wiring condition. Based on the pieces of wiring information thus generated, there are automatically generated circuit data of the circuit to be designed.

Abstract: An analyzing method for resource allocation and scheduling enhances simplification and speed-up of the process without employing a linear programming method, but based on an experimental method. The method uses a network consisting of nodes and branches for a model of resource allocation. In a network composed of extracted strongly connected components, the weight of each branch is repeatedly determined so that the sum of the weight of the input branches is equal to the sum of the weight of the output branches at each node. Furthermore, a branch having the maximum weight is detected in the network, so that the nodes are scheduled.

Abstract: In network charts such as logic circuit diagrams, the present invention makes it possible to perform level assignment of nodes efficiently and universally. A method for assigning levels to nodes according to the present invention includes a first step of dividing a network chart or a logic circuit into strongly connected components, a second step of providing all arcs with weights for every node of the above described strongly connected components having at least two nodes so that the inflow of arc weight may become equivalent to the outflow thereof, a third step of detecting an arc for which the weight in the above described strongly connected component becomes the maximum, and a fourth step of determining a disconnection point of a loop out of arcs for which the above described weights become the maximum or becomes its proportionate magnitude. All loops included in the network chart are thus removed.

Abstract: A plurality of types of circuit transformation rules have condition parts and conclusion parts. An inference control knowledge includes a knowledge related to a method of inferring the circuit transformation rules and a knowledge related to a relation between the circuit transformation rules. The circuit transformation rules are compiled into circuit transformation programs by use of the inference control knowledge. Already-existing programs include a procedural process of a logic design and various functions necessary for an execution of the circuit transformation programs. The circuit transformation programs and the already-existing programs are combined into a logic design program. A circuit transformation process is executed in accordance with the logic design program.

Abstract: In a system for transforming input circuit information into information of a logic circuit composed of actual elements, a schematic diagram of a logic circuit composed of actual elements is displayed. A timing check is executed on the displayed logic circuit. A delay adjustment portion of the displayed schematic diagram is designated. A timing adjustment is executed by the system on the designated delay adjustment portion, and thereby the logic circuit is transformed into a second logic circuit composed of actual elements.

Abstract: This an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers.

Abstract: This invention discloses an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers.

Abstract: An apparatus and method for translating a function description of a circuit presented in hardware description language includes parsing the function description of the circuit to generate a parse tree. The structure of the parse tree is deformed to optimize the test level redundancy of the function description to thereby generate a deformed parse tree. The deformed parse tree is then translated into function blocks representing a hardware configuration of the circuit set forth by the function description.

Abstract: Circuit transformation of a first circuit constituted by a first set of elements into a logically equivalent second circuit constituted by a second set of elements is effected by selecting a candidate rule from a knowledge base memory. The knowledge base memory stores therein transformation rules expressed by a condition part and a conclusion part. The condition part of a candidate rule is matched to circuit data stored in a working memory. The application condition of the candidate rules is determined, and the candidate rule is applied to the circuit data of the working memory for transforming the circuit after confirmation of the establishment of the application condition. The knowledge base memory stores therein concise transformation rules including at least one of main transformation rules, subordinate transformation rules, logic negation rules and logic equivalence rules.

Abstract: A high speed arithmetic processor includes an array of arithmetic cells which operate on digits internally represented in a signed-digit binary format. Certain of these cells perform subtraction operations on two ordinary binary digits, and produce the difference in a 2-bit signed-digit binary format, without requiring a separate ordinary binary to signed-digit binary converter.

Abstract: In a case where an electronic circuit having the same function is to be realized by a different device, it is indispensable to prepare circuit diagrams conforming to devices and to utilize them for the job of circuit simulation or chip layout. When the circuit diagrams are to be automatically translated for the above purpose, translation rules become different depending upon the connective relations of an element to be translated, with other elements in the circuit or upon a function performed by the element. The present invention puts the rules into knowledge from the viewpoint of knowledge engineering and utilizes it thereby to realize the intended purpose.

Abstract: A high speed divider circuit which implements a shift/subtract division method utilizing signed-digital binary expressions for the internal operands includes a quotient determining circuit which determines the quotient digit from the partial remainder, and a pluarlity of arithmetic cells which determine successive quotient digits by subtracting the product of the divisor and the sequential digits from the sequential partial remainders. The arithmetic cells which process the two lowest significant digits, the cells which process the most significant digits, the cells which process the intermediate digits and the cells which determine the initial partial remainder are each specifically tailored to perform their respective functions and thereby result in a divider which requires fewer circuit elements, and is simpler to implement in an integrated circuit.

Abstract: An arithmetic processor and an addition/subtraction circuit therefor are disclosed. The arithmetic processor comprises a plurality of the addition/subtraction units arranged in parallel, each unit being capable of carrying out addition (or subtraction) with respect to respective digits of two operands. An addition/subtraction unit comprises a first circuit and a second circuit coupled to receive binary signals each representing a respective digit of the operands. At least a first of the two binary signals is a 2-bit signal representing a signed digit expression, one bit of which ("the sign bit") represents the sign of one of the digits of the operands and the other bit of which ("the magnitude bit") represents the magnitude of that one digit of the operands. The first circuit provides a binary signal representing an intermediate carry (or borrow) and the second circuit provides a binary signal representing an intermediate sum (or difference) from the two binary signals representing the digits of the operands.

Abstract: A high speed arithmetic processor which may compactly be fabricated on an LSI chip is disclosed. The arithmetic processor in a first-step arithmetic operation determines an intermediate carry (or intermediate borrow) for a higher order arithmetic operation from an internal operand such as augend (or minuend) and an addend (or subtrahend) for each digit in addition (or subtraction) of signed digit numbers, carried out as an internal arithmetic operation, and determines an intermediate sum (or intermediate difference). In a second step arithmetic operation, the processor obtains a final sum (or difference) for each digit from the intermediate sum (or intermediate difference) obtained in the first step arithmetic operation and an intermediate carry (or intermediate borrow) from a lower order arithmetic operation.

Abstract: An arithmetic processor cable of performing successive multiplication operations at high speeds is described in which the resultant product, internally represented as a carry-save or signed-digit expression, may be directly input in that form as the multiplier for the next successive multiplication operation. Additionally, a multiplier recoder circuit is provided which recodes the binary multiplier, in the form of a carry-save or signed-digit expression into a radix 4 signed-digit number, in order to further increase the operating speed.

Abstract: A high speed arithmetic processor and adder circuitry thereof are disclosed in which carry (borrow) propagation is never more than one digit. Addition (or subtraction) are performed by: (a) determining an intermediate carry (or borrow) at the i-th order position and an intermediate sum (or difference) at the i-th order position from the addend (or subtrahend) and the augend (or minuend) and (b) determining the sum (or difference) of the intermediate sum (or difference) at the i-th order position and the intermediate carry (or borrow) at the (i-1)-th or next-lower-order position. Logic equations, truth tables and circuitry are disclosed for implementing several embodiments of the invention.

Abstract: An arithmetic processor is disclosed for performing arithmetic operations utilizing an arithmetic operand represented by a signed digit expression having a plurality of digits which may have a positive, zero or negative value.

Abstract: A high speed processor including a multiplier is disclosed. The multiplier includes a multiplier recorder circuit which may record multipliers in groups of digits, and intermediate partial product generators which generate partial products from the recorded digits and a multiplicand. Addition/subtraction is then carried out on the intermediate partial products generated by the partial product generators. The processor may operate using signed digit expressions.