Patents by Inventor Tang-Yuan CHEN

Tang-Yuan CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11164756
    Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: November 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Xu Lu, Tang-Yuan Chen, Jin-Yuan Lai, Tse-Chuan Chou, Meng-Kai Shih, Shin-Luh Tarng
  • Publication number: 20210327796
    Abstract: A wiring structure is provided. The wiring structure includes an upper redistribution structure, a lower redistribution structure, a conductive structure, an upper bonding layer and a lower bonding layer. The conductive structure is disposed between and electrically connected to the upper redistribution structure and the lower redistribution structure. The upper bonding layer is disposed between the upper redistribution structure and the conductive structure to bond the upper redistribution structure and the conductive structure together. The lower bonding layer is disposed between the lower redistribution structure and the conductive structure to bond the lower redistribution structure and the conductive structure together.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Chih-Pin HUNG
  • Publication number: 20210288024
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 16, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
  • Publication number: 20210280744
    Abstract: A semiconductor device package includes a carrier, an emitting element and a first package body. The carrier includes a first surface and a second surface opposite to the first surface. The emitting element is disposed on the first surface of the carrier. The first package body is disposed over the first surface of the carrier and spaced apart from the first surface of the carrier.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Wei HSIEH, Cheng-Yuan KUNG
  • Patent number: 11011496
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: May 18, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
  • Publication number: 20210074676
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Meng-Kai SHIH, Teck-Chong LEE, Shin-Luh TARNG, Chih-Pin HUNG
  • Publication number: 20200381338
    Abstract: A semiconductor device package includes a carrier, an electronic component, a package body and a ring structure. The electronic component is disposed on the carrier. The electronic component has a side surface. The package body is disposed on the carrier. The package body exposes at least a portion of the side surface of the electronic component. The ring structure is disposed on the package body and surrounds the portion of the side surface of the electronic component exposed from the package body.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Tang-Yuan CHEN, Yuan Tzuo LUO, Shao-Cheng YEN, Meng-Kai SHIH, Chih-Pin HUNG
  • Patent number: 10840219
    Abstract: A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: November 17, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bo-Syun Chen, Tang-Yuan Chen, Yu-Chang Chen, Jin-Feng Yang, Chin-Li Kao, Meng-Kai Shih
  • Patent number: 10770369
    Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: September 8, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Pin Hung, Tang-Yuan Chen, Jin-Feng Yang, Meng-Kai Shih
  • Publication number: 20200211863
    Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ying-Xu LU, Tang-Yuan CHEN, Jin-Yuan LAI, Tse-Chuan CHOU, Meng-Kai SHIH, Shin-Luh TARNG
  • Patent number: 10586716
    Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: March 10, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ying-Xu Lu, Tang-Yuan Chen, Jin-Yuan Lai, Tse-Chuan Chou, Meng-Kai Shih, Shin-Luh Tarng
  • Publication number: 20200066612
    Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.
    Type: Application
    Filed: August 24, 2018
    Publication date: February 27, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chih-Pin HUNG, Tang-Yuan CHEN, Jin-Feng YANG, Meng-Kai SHIH
  • Publication number: 20190287947
    Abstract: A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Bo-Syun CHEN, Tang-Yuan CHEN, Yu-Chang CHEN, Jin-Feng YANG, Chin-Li KAO, Meng-Kai SHIH
  • Patent number: 10332862
    Abstract: A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 25, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bo-Syun Chen, Tang-Yuan Chen, Yu-Chang Chen, Jin-Feng Yang, Chin-Li Kao, Meng-Kai Shih
  • Publication number: 20190074264
    Abstract: A semiconductor package structure includes a first substrate, at least one first semiconductor element and a second substrate. The first semiconductor element is attached to the first substrate. The second substrate defines a cavity and includes a plurality of thermal vias. One end of each of the thermal vias is exposed in the cavity, and the first semiconductor element is disposed within the cavity and thermally connected to the thermal vias.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 7, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Bo-Syun CHEN, Tang-Yuan CHEN, Yu-Chang CHEN, Jin-Feng YANG, Chin-Li KAO, Meng-Kai SHIH
  • Patent number: 10217649
    Abstract: A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: February 26, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Jin-Yuan Lai, Tang-Yuan Chen, Ying-Xu Lu, Dao-Long Chen, Kwang-Lung Lin, Chih-Pin Hung, Tse-Chuan Chou, Ming-Hung Chen, Chi-Hung Pan
  • Publication number: 20180358238
    Abstract: The present disclosure relates to a semiconductor device package comprising a substrate, a semiconductor device, and a underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Inventors: Jin-Yuan LAI, Tang-Yuan CHEN, Ying-Xu LU, Dao-Long CHEN, Kwang-Lung LIN, Chih-Pin HUNG, Tse-Chuan CHOU, Ming-Hung CHEN, Chi-Hung PAN
  • Publication number: 20180358237
    Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.
    Type: Application
    Filed: June 9, 2017
    Publication date: December 13, 2018
    Inventors: Ying-Xu LU, Tang-Yuan CHEN, Jin-Yuan LAI, Tse-Chuan CHOU, Meng-Kai SHIH, Shin-Lih TARNG
  • Patent number: 9589871
    Abstract: The present disclosure relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a leadframe and a semiconductor die. The leadframe includes a main portion and a protrusion portion. The semiconductor die is bonded to a first surface of the main portion. The protrusion portion protrudes from a second surface of the main portion. The position of the protrusion portion corresponds to the position of the semiconductor die.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: March 7, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Chin-Li Kao, Kuo-Hua Chen, Ming-Hung Chen, Dao-Long Chen
  • Patent number: 9478500
    Abstract: Described herein are interposer substrate designs for warpage control, semiconductor structures including said interposer substrates, and fabricating processes thereof. An interposer substrate defines a cavity and further includes a reinforcement structure, wherein the reinforcement structure is used to control warpage of the semiconductor package structure.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: October 25, 2016
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Ching Chen, Chin-Li Kao, Hung-Jen Chang, Tang-Yuan Chen, Wei-Hong Lai